From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40628C433F5 for ; Mon, 27 Aug 2018 09:10:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D13E7208D6 for ; Mon, 27 Aug 2018 09:10:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D13E7208D6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726971AbeH0Mzq (ORCPT ); Mon, 27 Aug 2018 08:55:46 -0400 Received: from foss.arm.com ([217.140.101.70]:48730 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726802AbeH0Mzp (ORCPT ); Mon, 27 Aug 2018 08:55:45 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B35327A9; Mon, 27 Aug 2018 02:09:57 -0700 (PDT) Received: from big-swifty.misterjones.org (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E23E53F5BD; Mon, 27 Aug 2018 02:09:54 -0700 (PDT) Date: Mon, 27 Aug 2018 10:09:50 +0100 Message-ID: <867ekcxjj5.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Jia He Cc: Thomas Gleixner , Jason Cooper , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jia He Subject: Re: [PATCH] irqchip/gic-v3-its: add allocation max order limitation for lpi_id_bits In-Reply-To: <81286c7a-8e16-0925-7646-7d422d10114f@gmail.com> References: <1535274051-2418-1-git-send-email-jia.he@hxt-semitech.com> <868t4tx88w.wl-marc.zyngier@arm.com> <81286c7a-8e16-0925-7646-7d422d10114f@gmail.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 27 Aug 2018 02:41:04 +0100, Jia He wrote: > > Hi Marc > Thanks for the comments > > On 8/27/2018 3:01 AM, Marc Zyngier Wrote: > > [I'm travelling, so expect some major delays in responding to email] > > > > Hi Jia, > > > > On Sun, 26 Aug 2018 10:00:51 +0100, > > Jia He wrote: > >> > >> There is a WARN_ON when my QDF2400 server boots up (pagesize is 4k) > > > > [snip] > > > >> In its_alloc_lpi_tables, lpi_id_bits is 24, without this patch, > >> its_allocate_prop_table will try to allocate 16M(order 12 if > >> pagesize=4k). Thus it causes the WARN_ON. > > > > Gah! QDF and its 24bit INTIDs... Making life hell for everyone ;-) > > > > Sorry for breaking it. > > np, maybe QDF2400 is a little bit special > > > > >> > >> This patch fixes it by limiting the lpi_id_bits. > >> > >> Signed-off-by: Jia He > >> --- > >> drivers/irqchip/irq-gic-v3-its.c | 5 ++++- > >> 1 file changed, 4 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c > >> index 316a575..79e6993 100644 > >> --- a/drivers/irqchip/irq-gic-v3-its.c > >> +++ b/drivers/irqchip/irq-gic-v3-its.c > >> @@ -1624,8 +1624,11 @@ static void its_free_prop_table(struct page *prop_page) > >> static int __init its_alloc_lpi_tables(void) > >> { > >> phys_addr_t paddr; > >> + u32 max_bits; /*max order limitation in alloc_page*/ > >> > >> - lpi_id_bits = GICD_TYPER_ID_BITS(gic_rdists->gicd_typer); > >> + max_bits = PAGE_SHIFT + MAX_ORDER - 1; > >> + lpi_id_bits = min_t(u32, max_bits, > >> + GICD_TYPER_ID_BITS(gic_rdists->gicd_typer)); > >> gic_rdists->prop_page = its_allocate_prop_table(GFP_NOWAIT); > >> if (!gic_rdists->prop_page) { > >> pr_err("Failed to allocate PROPBASE\n"); > >> -- > >> 1.8.3.1 > >> > > > > I find it rather odd that we end-up with different interrupt ranges > > depending on the CPU page size. Also, allocating that much memory for > > LPIs is rather pointless, as we actually have a pretty low limit of > > interrupts the system can deal with (see IRQ_BITMAP_BITS, which is > > slightly more than 8k). I've so far seen *one* request to push it up, > > but I doubt that it is a real use case. > > > > Capping lpi_id_bits at 16 (which is what we had before) is plenty, > > will save a some memory, and gives some margin before we need to push > > it up again. > > Do you want me to revert commit fe8e93504 to cap the lpi_id_bits > to no greater than ITS_MAX_LPI_NRBITS(16) instead this patch? Yes, this is probably the best course of action at this time. When I dropped this, I was mostly thinking of the LPI allocator (which now works with an almost constant memory footprint), and didn't pay enough attention to the property table allocation (which is still a function of the number of LPIs). Thanks, M. -- Jazz is not dead, it just smell funny.