From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA8B5C282CB for ; Mon, 28 Jan 2019 09:59:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9028A2087E for ; Mon, 28 Jan 2019 09:59:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726820AbfA1J7E (ORCPT ); Mon, 28 Jan 2019 04:59:04 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:42538 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726369AbfA1J7D (ORCPT ); Mon, 28 Jan 2019 04:59:03 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4CF59EBD; Mon, 28 Jan 2019 01:59:03 -0800 (PST) Received: from big-swifty.misterjones.org (big-swifty.cambridge.arm.com [10.1.39.122]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7B0103F589; Mon, 28 Jan 2019 01:59:00 -0800 (PST) Date: Mon, 28 Jan 2019 09:58:59 +0000 Message-ID: <86a7jlw1b0.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Julien Thierry Cc: , , , , , , , , , Subject: Re: [PATCH v9 10/26] arm64: kvm: Unmask PMR before entering guest In-Reply-To: <1548084825-8803-11-git-send-email-julien.thierry@arm.com> References: <1548084825-8803-1-git-send-email-julien.thierry@arm.com> <1548084825-8803-11-git-send-email-julien.thierry@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 21 Jan 2019 15:33:29 +0000, Julien Thierry wrote: > > Interrupts masked by ICC_PMR_EL1 will not be signaled to the CPU. This > means that hypervisor will not receive masked interrupts while running a > guest. > > Avoid this by making sure ICC_PMR_EL1 is unmasked when we enter a guest. > > Signed-off-by: Julien Thierry > Acked-by: Catalin Marinas > Cc: Christoffer Dall > Cc: Marc Zyngier > Cc: Catalin Marinas > Cc: Will Deacon > Cc: kvmarm@lists.cs.columbia.edu > --- > arch/arm64/include/asm/kvm_host.h | 12 ++++++++++++ > arch/arm64/kvm/hyp/switch.c | 16 ++++++++++++++++ > 2 files changed, 28 insertions(+) > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index 7732d0b..a1f9f55 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -24,6 +24,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -474,6 +475,17 @@ static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) > static inline void kvm_arm_vhe_guest_enter(void) > { > local_daif_mask(); > + > + /* > + * Having IRQs masked via PMR when entering the guest means the GIC > + * will not signal the CPU of interrupts of lower priority, and the > + * only way to get out will be via guest exceptions. > + * Naturally, we want to avoid this. > + */ > + if (system_uses_irq_prio_masking()) { > + gic_write_pmr(GIC_PRIO_IRQON); > + dsb(sy); > + } > } > > static inline void kvm_arm_vhe_guest_exit(void) > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c > index b0b1478..6a4c2d6 100644 > --- a/arch/arm64/kvm/hyp/switch.c > +++ b/arch/arm64/kvm/hyp/switch.c > @@ -22,6 +22,7 @@ > > #include > > +#include > #include > #include > #include > @@ -521,6 +522,17 @@ int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu) > struct kvm_cpu_context *guest_ctxt; > u64 exit_code; > > + /* > + * Having IRQs masked via PMR when entering the guest means the GIC > + * will not signal the CPU of interrupts of lower priority, and the > + * only way to get out will be via guest exceptions. > + * Naturally, we want to avoid this. > + */ > + if (system_uses_irq_prio_masking()) { > + gic_write_pmr(GIC_PRIO_IRQON); > + dsb(sy); > + } > + > vcpu = kern_hyp_va(vcpu); > > host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); > @@ -573,6 +585,10 @@ int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu) > */ > __debug_switch_to_host(vcpu); > > + /* Returning to host will clear PSR.I, remask PMR if needed */ > + if (system_uses_irq_prio_masking()) > + gic_write_pmr(GIC_PRIO_IRQOFF); > + > return exit_code; > } It'd be good to have helpers for these PMR manipulations, which I suspect you could use in other parts of the code such as patch #9. The logic itself seems good to me, so irrespective of the above: Reviewed-by: Marc Zyngier M. -- Jazz is not dead, it just smell funny.