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Fri, 04 Oct 2024 17:34:14 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 494HYDAI017938 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 4 Oct 2024 17:34:13 GMT Received: from [10.226.59.182] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 10:34:12 -0700 Message-ID: <86c8f688-eea3-ff95-5ae5-2e4da32b7edb@quicinc.com> Date: Fri, 4 Oct 2024 11:34:11 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.0 Subject: Re: [PATCH V3 03/11] accel/amdxdna: Support hardware mailbox Content-Language: en-US To: Lizhi Hou , , CC: , , , , , George Yang References: <20240911180604.1834434-1-lizhi.hou@amd.com> <20240911180604.1834434-4-lizhi.hou@amd.com> From: Jeffrey Hugo In-Reply-To: <20240911180604.1834434-4-lizhi.hou@amd.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: pq6_GxgSWdVfz9auUSD_XKmOQEBUVoBk X-Proofpoint-ORIG-GUID: pq6_GxgSWdVfz9auUSD_XKmOQEBUVoBk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040120 On 9/11/2024 12:05 PM, Lizhi Hou wrote: > +struct create_ctx_req { > + __u32 aie_type; > + __u8 start_col; > + __u8 num_col; > + __u16 reserved; > + __u8 num_cq_pairs_requested; > + __u8 reserved1; > + __u16 pasid; > + __u32 pad[2]; > + __u32 sec_comm_target_type; > + __u32 context_priority; Alignment > +} __packed; > + > +struct create_ctx_resp { > + enum aie2_msg_status status; > + __u32 context_id; > + __u16 msix_id; > + __u8 num_cq_pairs_allocated; > + __u8 reserved; > + struct cq_pair cq_pair[MAX_CQ_PAIRS]; > +} __packed; > + > +struct destroy_ctx_req { > + __u32 context_id; > +} __packed; > + > +struct destroy_ctx_resp { > + enum aie2_msg_status status; > +} __packed; > + > +struct execute_buffer_req { > + __u32 cu_idx; > + __u32 payload[19]; > +} __packed; > + > +struct exec_dpu_req { > + __u64 inst_buf_addr; > + __u32 inst_size; > + __u32 inst_prop_cnt; > + __u32 cu_idx; Alignment > + __u32 payload[35]; > +} __packed; > + > diff --git a/drivers/accel/amdxdna/aie2_psp.c b/drivers/accel/amdxdna/aie2_psp.c > index c87ca322e206..ac5296f4f2ae 100644 > --- a/drivers/accel/amdxdna/aie2_psp.c > +++ b/drivers/accel/amdxdna/aie2_psp.c > @@ -8,6 +8,8 @@ > #include > #include > > +#include "amdxdna_mailbox.h" > +#include "amdxdna_pci_drv.h" > #include "aie2_pci.h" Doesn't look like alphabetical order to me. Also similar instances in the *_regs.c files below > > #define PSP_STATUS_READY BIT(31)