From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 453AF4477F3; Thu, 8 Oct 2026 13:19:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791465594; cv=none; b=IEwb+QGPTMh4DpPkKZASER9xlERTjlJsiUeo+AtAQV+3N+5AksD8CUpM7IVvFJ5N84PZqmdKSOJ9rjtuxsHzRvfzLa11nEDO+0BJRXp/UVYr1PdHJo4i5NxZYB2E3ll+2XyxBJYApg3fHzA8LI5iXziXznF3GKlb7czE8IfWl+c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791465594; c=relaxed/simple; bh=Y1N0da2kegigQ8XnH+Rgc8b6lSa5p5sPQcdcGu81xmU=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=CMxGTIZRGpeAwBeuX9jWvXFCeZ6NgfNjtqqKODRzEh0CNBpWgkQzdCHy3akfDF2nAPp//VP5x7SH6dR1gHV04t48B2EBFck/FzXxkVjFT9KxSXuXKZuUhSG1CGjPrCozUVxBmaF89Yv571CJTiKOftuV6a0Nbxrw3URhYTUX1jk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VCNagyWk; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VCNagyWk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D318D1F00893; Thu, 8 Oct 2026 13:19:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1791465592; bh=nRpIXXch9ORQvuMM32Uo3H+Arh+KSndx0M1M1TwYHmY=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=VCNagyWkpdc/kZY1NXXy8RKIG2UiqEzSGeTtBxTaWA7fGJJDTRv04PeuwS9qkfGY1 4dt3v0L11ublrsxPjdn4YXd+ZdZe4XVJL1knvLkNegcuTU/hK66V4H5UjDry4PcVHk g96rBvrPiC1GQl603/yaNg34+GyDnp1PVb0COBrg7tW5PDzcWOpHyu0S58lMFuEcrx ReKALCyq4nuyOnO2K+u1ZhuIZB14KExlAvUmjprpmm1a8v0rjP9HfV73AOKw2u3Fbk c59/9lTc06+UwbWfWmg7/9EQXg7p4cOSjeWsMkLo1OevnzSb2vnjZ9nra6tRVdu1CE 7ZMhy4kmw/4zw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1xEo2I-00000000dqq-0E5U; Thu, 08 Oct 2026 13:19:50 +0000 Date: Thu, 08 Oct 2026 14:19:49 +0100 Message-ID: <86cxtk2utm.wl-maz@kernel.org> From: Marc Zyngier To: michael.reeves077@gmail.com Cc: Oliver Upton , Catalin Marinas , Will Deacon , Mark Rutland , Myria Sarvay , Yureka Lilian , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, Sven Peter , Janne Grunau , Neal Gompa , asahi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4 In-Reply-To: <20261008-apple-m3-m4-kvm-v1-2-7bb4cbf3d63b@gmail.com> References: <20261008-apple-m3-m4-kvm-v1-0-7bb4cbf3d63b@gmail.com> <20261008-apple-m3-m4-kvm-v1-2-7bb4cbf3d63b@gmail.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: michael.reeves077@gmail.com, oupton@kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, myrialsarvay@gmail.com, yureka@cyberchaos.dev, fuad.tabba@linux.dev, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, sven@kernel.org, j@jannau.net, neal@gompa.dev, asahi@lists.linux.dev, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Hi Michael, On Thu, 08 Oct 2026 13:15:41 +0100, Michael Reeves via B4 Relay wrote: > > From: Michael Reeves > > Add M3, M3 Pro, M3 Max and base M4 to apple_cpus so they receive the > existing PMU trap and broken SEIS workarounds needed by KVM. > How have you established that these CPUs suffer from the same SEIS erratum? I'm all for working around bugs, but I'd like to make sure the new fancy stuff is indeed just as broken as the old shit... For the record, the EDKII build in the QEMU EFI package that was in part of Debian Bullseye was able to trigger the bug semi reliably (series of writes to ICC_EOIR1_EL1 for interrupts that were never active). This happens on handover to the guest kernel. I can provide the binary (and a few scripts) to test this easily. Should they have been fixed, we can always create a second implementation list to cover the PMU. Thanks, M. -- Without deviation from the norm, progress is not possible.