From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 249AFC43142 for ; Tue, 31 Jul 2018 06:15:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D7CFC20862 for ; Tue, 31 Jul 2018 06:15:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D7CFC20862 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731500AbeGaHyJ (ORCPT ); Tue, 31 Jul 2018 03:54:09 -0400 Received: from foss.arm.com ([217.140.101.70]:48538 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727308AbeGaHyI (ORCPT ); Tue, 31 Jul 2018 03:54:08 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 70BF280D; Mon, 30 Jul 2018 23:15:30 -0700 (PDT) Received: from big-swifty.misterjones.org (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 661CC3F2EA; Mon, 30 Jul 2018 23:15:26 -0700 (PDT) Date: Tue, 31 Jul 2018 07:15:22 +0100 Message-ID: <86d0v4x75x.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Thomas Gleixner Cc: Bjorn Helgaas , Heiner Kallweit , Bjorn Helgaas , , Christoph Hellwig , LKML Subject: Re: [PATCH] PCI: let pci_request_irq properly deal with threaded interrupts In-Reply-To: References: <20180730213028.GC45322@bhelgaas-glaptop.roam.corp.google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 30 Jul 2018 23:36:57 +0100, Thomas Gleixner wrote: > > On Mon, 30 Jul 2018, Bjorn Helgaas wrote: > > > [+cc Thomas, Christoph, LKML] > > + Marc > > > On Mon, Jul 30, 2018 at 12:03:42AM +0200, Heiner Kallweit wrote: > > > If we have a threaded interrupt with the handler being NULL, then > > > request_threaded_irq() -> __setup_irq() will complain and bail out > > > if the IRQF_ONESHOT flag isn't set. Therefore check for the handler > > > being NULL and set IRQF_ONESHOT in this case. > > > > > > This change is needed to migrate the mei_me driver to > > > pci_alloc_irq_vectors() and pci_request_irq(). > > > > > > Signed-off-by: Heiner Kallweit > > > > I'd like an ack from Thomas because this requirement about IRQF_ONESHOT > > usage isn't mentioned in the request_threaded_irq() function doc or > > Documentation/ > > Right. The documentation really needs some love and care. :( > > Yes, request for pure threaded interrupts are rejected if the oneshot flag > is not set. The reason is that this would be deadly especially with level > triggered interrupts because the primary default handler just wakes the > thread and then reenables interrupts, which will make the interrupt come > back immediately and the thread won't have a chance to actually shut it up > in the device. > > That made me look into that code again and I found that we added a flag for > irq chips to tell the core that the interrupt is one shot safe, i.e. that > it can be requested w/o IRQF_ONESHOT. That was initially added to optimize > MSI based interrupts which are oneshot safe by implementation. > > dc9b229a58dc ("genirq: Allow irq chips to mark themself oneshot safe") > > The original patch added that flag to the x86 MSI irqchip code, but that > part was not applied for reasons which slipped from memory. It might be > worthwhile to revisit that in order to avoid the mask/unmask overhead for > such cases. Yup, that would actually be beneficial to a range of interrupt controllers (only an obscure GPIO driver makes use of this flag). We could also consider extending this to support interrupt hierarchies, as __setup_irq() seems only concerned with the top of the stack (an IRQ provided by a generic MSI stack and backed by an irqchip providing IRQCHIP_ONESHOT_SAFE would go unnoticed). M. -- Jazz is not dead, it just smell funny.