From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by aws-us-west-2-korg-lkml-1.web.codeaurora.org (Postfix) with ESMTP id C185BC5CFF1 for ; Tue, 12 Jun 2018 16:34:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 81846208B4 for ; Tue, 12 Jun 2018 16:34:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 81846208B4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934663AbeFLQeL convert rfc822-to-8bit (ORCPT ); Tue, 12 Jun 2018 12:34:11 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:35916 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934543AbeFLQeJ (ORCPT ); Tue, 12 Jun 2018 12:34:09 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D54311529; Tue, 12 Jun 2018 09:34:08 -0700 (PDT) Received: from big-swifty.misterjones.org (big-swifty.cambridge.arm.com [10.1.27.191]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 73AA53F318; Tue, 12 Jun 2018 09:34:06 -0700 (PDT) Date: Tue, 12 Jun 2018 17:34:03 +0100 Message-ID: <86d0ww7ymc.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Srinivas Kandagatla Cc: tglx@linutronix.de, jason@lakedaemon.net, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, bjorn.andersson@linaro.org, sboyd@kernel.org Subject: Re: [PATCH] irqchip/gic-v3: do not access GICR_WAKER if its secured register. In-Reply-To: <20180612145516.30897-1-srinivas.kandagatla@linaro.org> References: <20180612145516.30897-1-srinivas.kandagatla@linaro.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 12 Jun 2018 15:55:16 +0100, Srinivas Kandagatla wrote: > > GICR_WAKER can be a secured register, check this before accessing it > as its done in power management code. NAK. >From the GICv3 spec: * When GICD_CTLR.DS==1, this register is always accessible. * When GICD_CTLR.DS==0, this is a Secure register. This register is RAZ/WI to Non-secure accesses. > Without this patch Qualcomm DB820c board crashes. I suggest you find out how the GIC has been integrated on this platform. If you take a fault on accessing this register, this very much looks like an integration bug, and it should be quirked as such. Thanks, M. > > Signed-off-by: Srinivas Kandagatla > --- > drivers/irqchip/irq-gic-v3.c | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 5a67ec084588..38136d6e9ca5 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -656,6 +656,12 @@ static int gic_dist_supports_lpis(void) > return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && !gicv3_nolpi; > } > > +/* Check whether it's single security state view */ > +static bool gic_dist_security_disabled(void) > +{ > + return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; > +} > + > static void gic_cpu_init(void) > { > void __iomem *rbase; > @@ -664,7 +670,8 @@ static void gic_cpu_init(void) > if (gic_populate_rdist()) > return; > > - gic_enable_redist(true); > + if (gic_dist_security_disabled()) > + gic_enable_redist(true); > > rbase = gic_data_rdist_sgi_base(); > > @@ -819,11 +826,6 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, > #endif > > #ifdef CONFIG_CPU_PM > -/* Check whether it's single security state view */ > -static bool gic_dist_security_disabled(void) > -{ > - return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; > -} > > static int gic_cpu_pm_notifier(struct notifier_block *self, > unsigned long cmd, void *v) > -- > 2.16.2 > -- Jazz is not dead, it just smell funny.