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[72.83.177.149]) by smtp.gmail.com with ESMTPSA id r2-20020ae9d602000000b006ceb933a9fesm4946019qkk.81.2022.10.19.08.13.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Oct 2022 08:13:28 -0700 (PDT) Message-ID: <86e2a49b-557a-0a91-3e54-e64115fec736@linaro.org> Date: Wed, 19 Oct 2022 11:13:27 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: Re: [PATCH 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge Content-Language: en-US To: Thippeswamy Havalige , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: bhelgaas@google.com, michals@xilinx.com, robh+dt@kernel.org, bharat.kumar.gogada@amd.com References: <20221019144640.9458-1-thippeswamy.havalige@amd.com> <20221019144640.9458-2-thippeswamy.havalige@amd.com> From: Krzysztof Kozlowski In-Reply-To: <20221019144640.9458-2-thippeswamy.havalige@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 19/10/2022 10:46, Thippeswamy Havalige wrote: > Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge > dt binding. > > Signed-off-by: Thippeswamy Havalige (...) > diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.yaml > new file mode 100644 > index 000000000000..97a33e8cc171 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.yaml > @@ -0,0 +1,122 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/xilinx-nwl-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx NWL PCIe Root Port Bridge DT description Same comments apply. > + > +maintainers: > + - Thippeswamy Havalige Use current email address. > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + > +properties: > + compatible: > + const: xlnx,nwl-pcie-2.11 > + > + reg: > + items: > + - description: PCIe bridge registers location. > + - description: PCIe Controller registers location. > + - description: PCIe Configuration space region. > + > + reg-names: > + items: > + - const: breg > + - const: pcireg > + - const: cfg > + > + interrupts: > + items: > + - description: msi0 interrupt asserted when an MSI is received > + - description: msi1 interrupt asserted when an MSI is received > + - description: interrupt asserted when a legacy interrupt is received > + - description: unused interrupt(dummy) > + - description: interrupt asserted when miscellaneous interrupt is received > + > + interrupt-names: > + minItems: 5 maxItems instead > + > + interrupt-map-mask: > + items: > + - const: 0 > + - const: 0 > + - const: 0 > + - const: 7 > + > + "#interrupt-cells": > + const: 1 > + > + msi-controller: > + description: Identifies the node as an MSI controller. If it is a MSI controller, shouldn't you reference /schemas/interrupt-controller/msi-controller.yaml ? > + > + msi-parent: > + description: MSI controller the device is capable of using. msi-parent: true > + > + interrupt-map: > + maxItems: 4 > + > + legacy-interrupt-controller: > + description: Interrupt controller node for handling legacy PCI interrupts. > + type: object Same comments apply. > + properties: > + "#address-cells": > + const: 0 > + "#interrupt-cells": > + const: 1 > + "interrupt-controller": true > + what happened to clocks? You did not describe any changes in commit msg. > +required: compatible > + - reg > + - reg-names > + - interrupts > + - interrupt-names > + - "#interrupt-cells" > + - interrupt-map > + - msi-controller > + - msi-parent > + - interrupt-map-mask > + - legacy-interrupt-controller Drop properties required by referenced schema. > + > +unevaluatedProperties: false > + > +examples: > + - | > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + nwl_pcie: pcie@fd0e0000 { > + #address-cells = <3>; Mess up indentation Use 4 spaces for example indentation. > + #size-cells = <2>; > + compatible = "xlnx,nwl-pcie-2.11"; Same comments apply > + #interrupt-cells = <1>; > + msi-controller; > + device_type = "pci"; > + interrupt-parent = <&gic>; > + interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>; > + interrupt-names = "msi0", "msi1", "intx", "dummy", "misc"; > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, > + <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, > + <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, > + <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; > + > + msi-parent = <&nwl_pcie>; > + reg = <0x0 0xfd0e0000 0x0 0x1000>, > + <0x0 0xfd480000 0x0 0x1000>, > + <0x80 0x00000000 0x0 0x1000000>; This is a second property in the list (followed by reg-names, ranges) > + reg-names = "breg", "pcireg", "cfg"; > + ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000 > + 0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>; > + > + pcie_intc: legacy-interrupt-controller { > + interrupt-controller; That's even worse... > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + > + }; > + }; Best regards, Krzysztof