From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9748F41A76F; Sat, 3 Oct 2026 14:53:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791039216; cv=none; b=OIyv+uBDpdOJztmMWER7hrw572NTNr/73BP7ZtX2KcdQs5piMCmYZprM4nPz0xStEaCb6g+aQFy7OkHsbkB871DweFo/Fz6Q0uAnrNVIK81RM3Q+/6sAOezVcSw7Aj5jOZoN4HcIiq006uPIkN93XSSZY61zr0HzjuRoLYbMpps= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791039216; c=relaxed/simple; bh=lPPRuJSXZ04HyzQza9o8U1gXfmMmV67weXtXZvd53kg=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=PMwBzm9OGxBFpXoc1isEKvgvHRZrmSfmDvqKKzqmHcOtybR1BB4mQOhixUDAQpyAxvMAnWSx8zth/E6KSrAEra8pwRfLtJZy1m1lAnQtMSAKRpqNM5XgUubOM7U+viPtClOJDKa5Rh8AloLUHPwsM8F5AK34VcyYAn96vC00q4g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cLtAPnfQ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cLtAPnfQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 230A01F0089B; Sat, 3 Oct 2026 14:53:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1791039214; bh=l6e5SFKNalWkFlh1k64I5ENSGoQuN42StaikJNmYu/8=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=cLtAPnfQRzeVvQpcgjqON68hdJlGOOtb+HQOBeqRbacGFSAFTRUITk0/wliohlVT7 c7KIJlOZaonbgsobntYRapJmnt7vDZj8REwnScMH18aDGTJFC+v5mryxXGy0/krzba 2MeIQ0DzDoaZlAFt7rj4rTJY8pZI4SZ/4F5OpsqSSChAziFmJiMMDbqsDPzDeHGsCt 6Pa9/6rKR5n1Wr84E4vJqusAP8YVeGAqSNDr2o4Txhl0Jip5KJDLyLGN7+gRvg+0Am VXTr/V2jvauKeV+X4+nE2LCKp75mS0+GUWrbdlta3TyjCoSN/ZB6JjWPra7sd+xV1W PeiT91ayiDD3Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1xD17D-0000000GYMi-3OEA; Sat, 03 Oct 2026 14:53:31 +0000 Date: Sat, 03 Oct 2026 15:53:31 +0100 Message-ID: <86ece63kes.wl-maz@kernel.org> From: Marc Zyngier To: Yize Wang Cc: , , , , , , , , , , , , , Subject: Re: [PATCH 0/2] Batch register access for live migration optimization In-Reply-To: References: <20260918081930.4014735-1-wangyize7@huawei.com> <861paq69te.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: wangyize7@huawei.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, fuad.tabba@linux.dev, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, mark.rutland@arm.com, zhengchuan@huawei.com, jiangjiacheng@huawei.com, yize_w1110@163.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Sun, 20 Sep 2026 10:15:25 +0100, Yize Wang wrote: >=20 > =E5=9C=A8 2026/9/18 20:08, Marc Zyngier =E5=86=99=E9=81=93: > > On Fri, 18 Sep 2026 09:18:13 +0100, > > Yize Wang wrote: > >> This series adds batch register access support to KVM/arm64 to reduce > >> syscall overhead during VM live migration. > >>=20 > >> Currently, QEMU issues one ioctl per register when saving/restoring VG= IC > >> state. On large VM configurations this means tens of thousands of sysc= alls, > >> where lock acquisition and context switch overhead dominates migration > >> downtime. Thus, we provide a batch register method to allow userspace > >> read/write multiple distributor and redistributor registers in a singl= e call. > >> In this way, we can significantly reduce syscalls and migration downti= me. > >>=20 > >> Test the VM migration time under pressure conditions. > >> The VM specifications for migration are as follows: > >> - VM use 4-K page; > >> - the number of VCPU is 160; > >> - the total memory is 320Gigabit; > >> - use 'Redis SET-benchmark' to pressurize VM; > >>=20 > >> Performance results (3-run average, ms): > >> | Metric | Without patch | With patch | Improvement | > >> |---------------------|---------------|------------|-------------| > >> | Migration downtime | 536 | 321 | 40% | > >> | Source (total) | 344 | 230 | 33% | > >> | - VGIC put | 158 | 40 | 75% | > >> | - VGIC get | 120 | 19 | 84% | > >> | Destination (total) | 192 | 91 | 53% | > >> | - VGIC put | 132 | 27 | 80% | > >>=20 > >> Yize Wang (2): > >> KVM: arm64: Add batch group constant and data structure to UAPI hea= der > >> KVM: arm64: Add VGIC v3 batch register access implementation > > Questions: > >=20 > > - Why only the MMIO registers? > >=20 > > - Why not the sysregs? > >=20 > > - Why only the GIC? > >=20 > > - Why not all of the state? > >=20 > > - Where is the corresponding userspace code? > >=20 > > More importantly, since this is about batching system calls: > >=20 > > - Why can't this be done with io_uring instead? > >=20 > > M. >=20 >=20 > Hi, Marc! Thank you for the review. >=20 > =C2=A0 These patches focus on optimizing GICv3 register access during live > migration. We found that there are a large number of locks (kvm->lock, > vcpus, config_lock) in the GIC, these lock operations wil cost large > time waste. The batches of sysreg for vcpu optimization will come in > follow as a separate series. And let me address these questions one by > one. All these locks should be non-blocking by the time you save anything related to the GIC, because: - none of the vcpu can be running - this must be a single threaded operation So if you are seeing anything contended, this is either the sign of a bad KVM bug, or an indication that you are violating the above requirements. M. --=20 Without deviation from the norm, progress is not possible.