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Tue, 23 Jun 2026 07:30:01 -0700 (PDT) From: =?UTF-8?q?Gr=C3=A9goire=20Layet?= To: joel@jms.id.au, andrew@codeconstruct.com.au, lkundrak@v3.sk, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: andrew@lunn.ch, jacky_chou@aspeedtech.com, yh_chung@aspeedtech.com, ninad@linux.ibm.com, anirudhsriniv@gmail.com, linux-serial@vger.kernel.org, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Gr=C3=A9goire=20Layet?= Subject: [PATCH v3 7/7] ARM: dts: aspeed: g6: add aspeed,vuart-over-pci prop to vuart3 and 4 Date: Tue, 23 Jun 2026 14:25:45 +0000 Message-ID: <86fc0b2a105a16ceb301ba53fadd096877455bb8.1782224060.git.gregoire.layet@9elements.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The VUART 3 and 4 are VUART over PCI. This flag indicates this information. Signed-off-by: Grégoire Layet --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 7c02633f2bd6..2a19463b4c21 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -723,6 +723,7 @@ vuart3: serial@1e787800 { interrupts = ; clocks = <&syscon ASPEED_CLK_APB2>; no-loopback-test; + aspeed,vuart-over-pci; status = "disabled"; }; @@ -743,6 +744,7 @@ vuart4: serial@1e788800 { interrupts = ; clocks = <&syscon ASPEED_CLK_APB2>; no-loopback-test; + aspeed,vuart-over-pci; status = "disabled"; }; -- 2.54.0