From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8D0CC31E46 for ; Wed, 12 Jun 2019 07:35:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A0528206BA for ; Wed, 12 Jun 2019 07:35:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731382AbfFLHfy (ORCPT ); Wed, 12 Jun 2019 03:35:54 -0400 Received: from foss.arm.com ([217.140.110.172]:46516 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726778AbfFLHfx (ORCPT ); Wed, 12 Jun 2019 03:35:53 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 741552B; Wed, 12 Jun 2019 00:35:47 -0700 (PDT) Received: from big-swifty.misterjones.org (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B636F3F246; Wed, 12 Jun 2019 00:35:42 -0700 (PDT) Date: Wed, 12 Jun 2019 08:35:41 +0100 Message-ID: <86ftofgss2.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Thomas Gleixner Cc: Leonard Crestez , Abel Vesa , Lucas Stach , Mark Rutland , Abel Vesa , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Jacky Bai , Lorenzo Pieralisi , dl-linux-imx , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Carlo Caione Subject: Re: [RFC 0/2] Add workaround for core wake-up on IPI for i.MX8MQ In-Reply-To: References: <20190610121346.15779-1-abel.vesa@nxp.com> <20190610131921.GB14647@lakrids.cambridge.arm.com> <20190610132910.srd4j2gtidjeppdx@fsr-ub1664-175> <6f1052ea-623a-b2e8-9aa8-22aef5fab4ca@arm.com> <20190610135514.xd5myavjsloos2y3@fsr-ub1664-175> <7b86aa90-6d64-589c-f11e-d2ee6ab3fd54@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 12 Jun 2019 08:14:16 +0100, Thomas Gleixner wrote: > On Mon, 10 Jun 2019, Leonard Crestez wrote: > > On 6/10/2019 5:08 PM, Marc Zyngier wrote: > > > Nobody is talking about performance here. It is strictly about > > > correctness, and what I read about this system is that it cannot > > > reliably use cpuidle. > > My argument was that it's fine if PPIs and LPIs are broken as long as > > they're not used: > > > > * PPIs are only used for local timer which is not used for wakeup. > > Huch? The timer has to bring the CPU out of idle as any other > interrupt. They use a separate hack for that, pretending that the timer is stopped during idle (it isn't), and setup a broadcast timer when entering idle. That timer uses an interrupt that can wake-up the target CPU, and all is well in the world. Sort of. Of course, this breaks as PPIs are not only used by the timer, but also by a number of other HW bits (PMU, GIC, guest and hypervisor timers), and they don't have corresponding hacks to back them up. Thanks, M. -- Jazz is not dead, it just smells funny.