From: Marc Zyngier <marc.zyngier@arm.com>
To: Anup Patel <anup@brainfault.org>
Cc: Palmer Dabbelt <palmer@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Atish Patra <atish.patra@wdc.com>,
Christoph Hellwig <hch@infradead.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 0/4] IRQ affinity support in PLIC driver
Date: Thu, 14 Feb 2019 12:33:08 +0000 [thread overview]
Message-ID: <86h8d6sg6z.wl-marc.zyngier@arm.com> (raw)
In-Reply-To: <20190212125246.69239-1-anup@brainfault.org>
On Tue, 12 Feb 2019 12:52:42 +0000,
Anup Patel <anup@brainfault.org> wrote:
>
> This patchset primarily adds IRQ affinity support in PLIC driver and
> other improvements.
>
> It gives mechanism for explicitly route external interrupts to particular
> CPUs using smp_affinity attribute of each Linux IRQs. Also, we can now
> use IRQ balancer from kernel-space or user-space.
>
> The patchset is tested on QEMU virt machine. It is based on Linux-5.0-rc6
> and can be found at riscv_plic_irq_affinity_v6 branch of:
> https://github.com/avpatel/linux.git
Applied to irqchip-next.
Thanks,
M.
--
Jazz is not dead, it just smell funny.
prev parent reply other threads:[~2019-02-14 12:33 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-12 12:52 Anup Patel
2019-02-12 12:52 ` [PATCH v6 1/4] irqchip: sifive-plic: Pre-compute context hart base and enable base Anup Patel
2019-02-12 12:52 ` [PATCH v6 2/4] irqchip: sifive-plic: Add warning in plic_init() if handler already present Anup Patel
2019-02-12 12:52 ` [PATCH v6 3/4] irqchip: sifive-plic: Differentiate between PLIC handler and context Anup Patel
2019-02-12 12:52 ` [PATCH v6 4/4] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host Anup Patel
2019-02-14 12:33 ` Marc Zyngier [this message]
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