From: Marc Zyngier <maz@kernel.org>
To: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Cc: tglx@kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5] irqchip/gic-v3: Add Altera SoCFPGA Agilex5 GIC600 DMA32 erratum workaround
Date: Mon, 07 Sep 2026 09:56:48 +0100 [thread overview]
Message-ID: <86ik4h4ey7.wl-maz@kernel.org> (raw)
In-Reply-To: <fc927e43892b86200e157fa303b0d1dd344caffd.1788751033.git.adrian.ho.yin.ng@altera.com>
On Mon, 07 Sep 2026 09:22:59 +0100,
Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com> wrote:
>
> Agilex5 integrates GIC600 with an ACE-lite interface limited to a 32-bit
> address bus, so the ITS can only access the first 4 GB of physical address
> space. Register intel,socfpga-agilex5 on the existing
> dma_32bit_impaired_platforms list so ITS allocations use GFP_DMA32.
>
> The workaround is guarded by ALTERA_ERRATUM_AGILEX5_2_1_23, which is
> selected by ARCH_INTEL_SOCFPGA as all Agilex5 devices are affected.
>
> This limitation is documented as Agilex 5 ES Device Errata 2.1.23 (825514).
>
> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
M.
--
Without deviation from the norm, progress is not possible.
prev parent reply other threads:[~2026-09-07 8:56 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-07 8:22 Adrian Ng Ho Yin
2026-09-07 8:56 ` Marc Zyngier [this message]
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