From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73D99C4708E for ; Wed, 23 Nov 2022 13:32:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238225AbiKWNco (ORCPT ); Wed, 23 Nov 2022 08:32:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237948AbiKWNbd (ORCPT ); Wed, 23 Nov 2022 08:31:33 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50A788E2A9 for ; Wed, 23 Nov 2022 05:13:58 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 0362EB81FDE for ; Wed, 23 Nov 2022 13:13:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B890FC433D6; Wed, 23 Nov 2022 13:13:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1669209235; bh=y9f4lqeRCpiH5LbtYqo2O8Ic6S+ENQB8BPXqx1szLz4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=AiEemWIwFHpFKyiCepagiUND0MTDLr0ozhKd8Ler5vKOkRyU9v4M5PrZwqsE/8C1+ quB58iEa/evirNJsVkL8rIQLo8U0IGDD36Snt/aiK4Tn1v/KcsAV2B0/KOXOMLRjeL IdLkreEVUC6zNYqX0cQKztQeQIG4D68hcTYx/2UMg+1TgT2YpxJQyu+CdEr3htHfMP Le+2kd3q0RSD9iZrWhlA4PYYO8yLdIsD8Hz3spZW/+BiH5SPEDgFjYVoWh/SV6QMPj haJTQXJbolDsTHHkcwxHiD8fy7jN0EpLaTI5KQQED78+YYM4MhmsySH9w+cIp4/PXO +45rtfCKqqRtQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oxpZZ-0087sV-Fh; Wed, 23 Nov 2022 13:13:53 +0000 Date: Wed, 23 Nov 2022 13:13:52 +0000 Message-ID: <86ilj5oltb.wl-maz@kernel.org> From: Marc Zyngier To: Icenowy Zheng Cc: Thomas Gleixner , Palmer Dabbelt , Paul Walmsley , Samuel Holland , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH] irqchip/sifive-plic: drop quirk for two-cell variant In-Reply-To: <16d01eebc1693916fc74e1e75458d6c0f080cf37.camel@icenowy.me> References: <20221121042026.419383-1-uwu@icenowy.me> <86o7syoq4t.wl-maz@kernel.org> <16d01eebc1693916fc74e1e75458d6c0f080cf37.camel@icenowy.me> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: uwu@icenowy.me, tglx@linutronix.de, palmer@dabbelt.com, paul.walmsley@sifive.com, samuel@sholland.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 23 Nov 2022 12:38:56 +0000, Icenowy Zheng wrote: >=20 > =E5=9C=A8 2022-11-22=E6=98=9F=E6=9C=9F=E4=BA=8C=E7=9A=84 17:28 +0000=EF= =BC=8CMarc Zyngier=E5=86=99=E9=81=93=EF=BC=9A > > On Mon, 21 Nov 2022 04:20:26 +0000, > > Icenowy Zheng wrote: > > >=20 > > > As the special handling of edge-triggered interrupts are defined in > > > the > > > PLIC spec, we can assume it's not a quirk, but a feature of the > > > PLIC > > > spec; thus making it a quirk and use quirk-based codepath is not so > > > necessary. > >=20 > > It *is* necessary. > >=20 > > >=20 > > > Move to a #interrupt-cells-based practice which will allow both > > > device > > > trees without interrupt flags and with interrupt flags work for all > > > compatible strings. > >=20 > > No. You're tying together two unrelated concepts: > >=20 > > - Edges get dropped in some implementations (and only some). You can > > =C2=A0 argue that the architecture allows it, but I see it is an > > =C2=A0 implementation bug. >=20 > As the specification allows it, it's not an implementation bug -- and > for those which do not show this problem, it's possible that it's just > all using the same trigger type (e.g. Rocket). What are you against? The fact that this is flagged as a quirk? Honestly, I don't care about that. If we can fold all implementations into the same scheme, that's fine by me. >=20 > >=20 > > - The need for expressing additional information in the interrupt > > =C2=A0 specifier is not necessarily related to the above. Other interru= pt > > =C2=A0 controllers use extra cells to encode the interrupt affinity, for > > =C2=A0 example. >=20 > I think in these situations, if the interrupt controller does not > contain any special handling for edge interrupts, we can just describe > them as level ones in SW. No, that's utterly wrong. We don't describe an edge as level. Ever. >=20 > >=20 > > I want these two things to be kept separate. Otherwise, once we get > > some fancy ACPI support for RISCV (no, please...), we'll have to redo > > the whole thing... > >=20 > > > In addition, this addresses a stable version DT binding violation - > > > - > > > Linux v5.19 comes with "thead,c900-plic" with #interrupt-cells > > > defined to > > > be 1 instead of 2, this commit will allow DTs that complies to > > > Linux > > > v5.19 binding work (although no such DT is devliered to the public > > > now). > >=20 > > *That* is what should get fixed. >=20 > Supporting all stable versions' DT binding is our promise, I think. Absolutely. And I'm asking you to fix it. And only that. Thanks, M. --=20 Without deviation from the norm, progress is not possible.