From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 452CCC43144 for ; Fri, 22 Jun 2018 17:54:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 11091246F5 for ; Fri, 22 Jun 2018 17:54:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 11091246F5 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934148AbeFVRyb (ORCPT ); Fri, 22 Jun 2018 13:54:31 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:39238 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932973AbeFVRy3 (ORCPT ); Fri, 22 Jun 2018 13:54:29 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 62D8A14; Fri, 22 Jun 2018 10:54:29 -0700 (PDT) Received: from big-swifty.misterjones.org (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4B9963F557; Fri, 22 Jun 2018 10:54:27 -0700 (PDT) Date: Fri, 22 Jun 2018 18:54:16 +0100 Message-ID: <86k1qq7lmf.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Shameerali Kolothum Thodi Cc: "linux-kernel@vger.kernel.org" , Thomas Gleixner , Ard Biesheuvel , Shanker Donthineni , Laurentiu Tudor , Lei Zhang , Linuxarm Subject: Re: [PATCH 6/7] irqchip/gic-v3-its: Honor hypervisor enforced LPI range In-Reply-To: <5FC3163CFD30C246ABAA99954A238FA838706A1B@FRAEML521-MBX.china.huawei.com> References: <20180620135234.32101-1-marc.zyngier@arm.com> <20180620135234.32101-7-marc.zyngier@arm.com> <5FC3163CFD30C246ABAA99954A238FA838706A1B@FRAEML521-MBX.china.huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Shammer, On Fri, 22 Jun 2018 17:31:40 +0100, Shameerali Kolothum Thodi wrote: > > Hi Marc, > > > -----Original Message----- > > From: Marc Zyngier [mailto:marc.zyngier@arm.com] > > Sent: 20 June 2018 14:53 > > To: linux-kernel@vger.kernel.org > > Cc: Thomas Gleixner ; Ard Biesheuvel > > ; Shanker Donthineni > > ; Shameerali Kolothum Thodi > > ; MaJun ; > > Laurentiu Tudor ; Lei Zhang > > > > Subject: [PATCH 6/7] irqchip/gic-v3-its: Honor hypervisor enforced LPI range > > > > A recent extension to the GIC architecture allows a hypervisor to > > arbitrarily reduce the number of LPIs available to a guest, no > > matter what the GIC says about the valid range of IntIDs. > > > > Let's factor in this information when computing the number of > > available LPIs > > On our D05 board, this limits the lpis to 2 and results in MSI irq > alloc fails: > > [ 0.000000] ITS: Using hypervisor restricted LPI range [2] > .... > [ 10.543889] ixgbe 000a:11:00.1: Failed to allocate MSI interrupt, falling back to legacy. Error: -12 > > > Signed-off-by: Marc Zyngier > > --- > > drivers/irqchip/irq-gic-v3-its.c | 9 +++++++++ > > include/linux/irqchip/arm-gic-v3.h | 1 + > > 2 files changed, 10 insertions(+) > > > > diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c > > index 8c7e8c235faf..903ca1c19553 100644 > > --- a/drivers/irqchip/irq-gic-v3-its.c > > +++ b/drivers/irqchip/irq-gic-v3-its.c > > @@ -1525,8 +1525,17 @@ static int free_lpi_range(u32 base, u32 nr_lpis) > > static int __init its_lpi_init(u32 id_bits) > > { > > u32 lpis = (1UL << id_bits) - 8192; > > + u32 numlpis; > > int err; > > > > + numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer); > > + > > + if (numlpis > 1 && !WARN_ON(numlpis > lpis)) { > > + lpis = numlpis; > > + pr_info("ITS: Using hypervisor restricted LPI range [%u]\n", > > + lpis); > > + } > > I don't have the GICv3 extension doc, but did you intent to check for, > > if (numlpis > 2 && !WARN_ON(numlpis > lpis)) { > > as it looks like D05 returns 0 for bits 11-15 and that makes numlpis=2. Absolutely. This really is a silly bug, thanks for catching that one. I've pushed out an update on my irq/lpi-allocator branch. Thanks, M. -- Jazz is not dead, it just smell funny.