From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 494C0C282C8 for ; Mon, 28 Jan 2019 12:47:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2295420881 for ; Mon, 28 Jan 2019 12:47:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726778AbfA1MrA (ORCPT ); Mon, 28 Jan 2019 07:47:00 -0500 Received: from foss.arm.com ([217.140.101.70]:44956 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726647AbfA1MrA (ORCPT ); Mon, 28 Jan 2019 07:47:00 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8EAB980D; Mon, 28 Jan 2019 04:46:59 -0800 (PST) Received: from big-swifty.misterjones.org (big-swifty.cambridge.arm.com [10.1.39.122]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 11BC13F59C; Mon, 28 Jan 2019 04:46:56 -0800 (PST) Date: Mon, 28 Jan 2019 12:47:00 +0000 Message-ID: <86o981ueyj.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Julien Thierry Cc: , , , , , , , , Subject: Re: [PATCH v9 26/26] arm64: Enable the support of pseudo-NMIs In-Reply-To: <1548084825-8803-27-git-send-email-julien.thierry@arm.com> References: <1548084825-8803-1-git-send-email-julien.thierry@arm.com> <1548084825-8803-27-git-send-email-julien.thierry@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 21 Jan 2019 15:33:45 +0000, Julien Thierry wrote: > > Add a build option and a command line parameter to build and enable the > support of pseudo-NMIs. > > Signed-off-by: Julien Thierry > Suggested-by: Daniel Thompson > Cc: Catalin Marinas > Cc: Will Deacon > --- > Documentation/admin-guide/kernel-parameters.txt | 6 ++++++ > arch/arm64/Kconfig | 14 ++++++++++++++ > arch/arm64/kernel/cpufeature.c | 11 ++++++++++- > 3 files changed, 30 insertions(+), 1 deletion(-) > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt > index b799bcf..173e2cc 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -1197,6 +1197,12 @@ > to discrete, to make X server driver able to add WB > entry later. This parameter enables that. > > + enable_pseudo_nmi [ARM64] > + Enables support for pseudo-NMIs in the kernel. This > + requires both the kernel to be built with > + CONFIG_ARM64_PSEUDO_NMI and to be running on a > + platform with GICv3. > + > enable_timer_pin_1 [X86] > Enable PIN 1 of APIC timer > Can be useful to work around chipset bugs > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index a4168d3..8d84bfd 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -1328,6 +1328,20 @@ config ARM64_MODULE_PLTS > bool > select HAVE_MOD_ARCH_SPECIFIC > > +config ARM64_PSEUDO_NMI > + bool "Support for NMI-like interrupts" > + select CONFIG_ARM_GIC_V3 > + help > + Adds support for mimicking Non-Maskable Interrupts through the use of > + GIC interrupt priority. This support requires version 3 or later of > + Arm GIC. > + > + This high priority configuration for interrupts need to be s/need/needs/ > + explicitly enabled through the new kernel parameter It won't be new forever... ;-) > + "enable_pseudo_nmi". I'm not overly keen on this name. We already have "irqchip.gicv3_nolpi", so why not adopt something similar. "irqchip.gicv3_pseudo_nmi", taking a boolean value? > + > + If unsure, say N > + > config RELOCATABLE > bool > help > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index b530fb24..e66d778 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1207,10 +1207,19 @@ static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap) > #endif /* CONFIG_ARM64_PTR_AUTH */ > > #ifdef CONFIG_ARM64_PSEUDO_NMI > +static bool enable_pseudo_nmi; > + > +static int __init early_enable_pseudo_nmi(char *p) > +{ > + enable_pseudo_nmi = true; And if you're happy with the above, this becomes: return strtobool(p, &enable_pseudo_nmi); > + return 0; > +} > +early_param("enable_pseudo_nmi", early_enable_pseudo_nmi); > + > static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, > int scope) > { > - return false; > + return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); > } > #endif > > -- > 1.9.1 > Thanks, M. -- Jazz is not dead, it just smell funny.