From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793093556; b=HO74Tgbb2dwl/g6rHzk9Sa4oFZJPiOHh2hjvCybJzPRe1Irr6pQPuRLAG8hW9yG2dTd/ TRQs5emLRABT4dMhxjz0l8H6wePIBBnAdGzkyBzvfRiFQqmc7A6wdyIXUsE2eOMcB3CH0 UmirgdKZjFDbELsa+oTiOIlPyrlv+cMEdYupUUXgaKlyYikMNPFbmK3IrXA98wlp5iLrz ooutVodEeucaw+w7DeoW2zL+6CZGbiVj0KoBdYXnlzF5tHwNXuAGCUaSEsyBGiOFfQtZY BmynC9fzECMbWKCPuBaCcLLpfedZU9vNiRvm581WktQko6F/RSW6yRo9U7QeiA8xPhQ== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793093556; h=Received:DKIM-Signature:Received:Date:Message-ID:From:To:Cc:Subject: In-Reply-To:References:User-Agent:MIME-Version:Content-Type: X-SA-Exim-Connect-IP:X-SA-Exim-Rcpt-To:X-SA-Exim-Mail-From: X-SA-Exim-Scanned; bh=v8kRiQmXlExTl6nzzD7dQ3TcCyE/USPMyj+a4wHCWzg=; b=pDjauhEl0oNmVHHOvgpBcT5eUahMsaVDjQBOEN5hQC8K3ybKm1zJQ5uTCbdVuY4FJQBq xxxnYQY76Cx4YDMFmcWKcU59NjUKmiiUcJt4MB7MvVkCzdPud5lwSqXbTGU6NAHSkXBZd mV1u3oUN32Df9bTgaeQrRojmIeXw+BPyXqDZh9LJrnnQ/wShzVS2XMAwlxOTdl4W3zPo4 brFZv8L9U8NO3eeobrXqULwFQybcYZzhOo4TcMMaP3BEr2FGPSh62h0wyriFJ8GTCPwk+ IJu2rzO0xsKLxuyxag0KbcIr1yXnUHransBGaCgovtWnxea+cpnlreBJ3Lq1amB/j8Q== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=AoUlGtx+; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDD85606A31A; Tue, 27 Oct 2026 09:32:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=AoUlGtx+ Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5D1E41F01828; Tue, 27 Oct 2026 09:32:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793093555; bh=v8kRiQmXlExTl6nzzD7dQ3TcCyE/USPMyj+a4wHCWzg=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=AoUlGtx+436lsWzCJkKEElbkUxqyrXz3URLfAQlUCAt1e8rVctNX+G3ZGr1Ai5JuL aoHVtIUKxAttvjydnhGIGFCcRmN2ozbKEPJi5W7By5TussH7TgQ1nTBFzvu250fLQ4 rW7Vebvgegixr7+D14kXWn/2/q/xnR2w2DMSFZMoGJOtNKl4tZ3Jeq0fJiqLyFcxd9 3QM/enVtC9OiIFGLSl2E5k6946WFamOiYgHs9m3I4YP0fNb/jewpozC7gWgGtFc4p5 g7Mz20GRwOPpRMqVSveCv3ZPm3eZf8G7ug0MA/Dlw7wFJoMB3dQ9QyPhF690TVMkJe Dww6KduBsxwaA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1xLdXk-00000007cVr-3TKm; Tue, 27 Oct 2026 09:32:32 +0000 Date: Tue, 27 Oct 2026 09:32:32 +0000 Message-ID: <86wlr3xzdb.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: Oliver Upton , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Vincent Donnefort , kernel-team@android.com, linux-kernel@vger.kernel.org, Oculytic , Fuad Tabba Subject: Re: [PATCH 3/3] KVM: arm64: Disable host PMU counters for protected guests In-Reply-To: <20261027081147.498183-4-fuad.tabba@linux.dev> References: <20261027081147.498183-1-fuad.tabba@linux.dev> <20261027081147.498183-4-fuad.tabba@linux.dev> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: fuad.tabba@linux.dev, oupton@kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, vdonnefort@google.com, kernel-team@android.com, linux-kernel@vger.kernel.org, oculytic@gmail.com, tabba@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 27 Oct 2026 08:11:47 +0000, Fuad Tabba wrote: > > A protected guest has no PMU, and EL2 clears MDCR_EL2.HPME for it. > However, HPME has no effect, since __pkvm_vcpu_load() sets HPMN to cover > every event counter, and HPME never covers the cycle or instruction > counter. The counters the host has enabled therefore keep counting the > guest. > > Stop them in the world switch while a protected guest runs, reading > PMCNTENSET_EL0 rather than trusting the host-controlled events mask. > Gate this on a new per-CPU HAS_PMUV3 flag, since system_supports_pmuv3() > is false when the CPUs implement different PMU versions. > > Side channels are outside pKVM's threat model, so this is hardening > rather than a fix. > > Reported-by: Oculytic > Signed-off-by: Fuad Tabba > --- > arch/arm64/include/asm/kvm_host.h | 1 + > arch/arm64/kvm/debug.c | 4 +++- > arch/arm64/kvm/hyp/nvhe/switch.c | 24 ++++++++++++++++++++++++ > 3 files changed, 28 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index 1c6632216e327..7ecb55e5018eb 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -834,6 +834,7 @@ struct kvm_host_data { > #define KVM_HOST_DATA_FLAG_VCPU_IN_HYP_CONTEXT 4 > #define KVM_HOST_DATA_FLAG_L1_VNCR_MAPPED 5 > #define KVM_HOST_DATA_FLAG_HAS_BRBE 6 > +#define KVM_HOST_DATA_FLAG_HAS_PMUV3 7 > unsigned long flags; > > struct kvm_cpu_context host_ctxt; > diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c > index f4d7b12045e8f..3c74b076b5278 100644 > --- a/arch/arm64/kvm/debug.c > +++ b/arch/arm64/kvm/debug.c > @@ -79,9 +79,11 @@ void kvm_init_host_debug_data(void) > unsigned int pmuver = cpuid_feature_extract_unsigned_field(dfr0, > ID_AA64DFR0_EL1_PMUVer_SHIFT); > > - if (pmuv3_implemented(pmuver)) > + if (pmuv3_implemented(pmuver)) { > *host_data_ptr(nr_event_counters) = FIELD_GET(ARMV8_PMU_PMCR_N, > read_sysreg(pmcr_el0)); > + host_data_set_flag(HAS_PMUV3); Honestly, I don't think we need to work out which CPUs have PMUv3 and which don't. I'd be perfectly happy to disable KVM on asymmetric systems, simply because they don't exist. M. -- Without deviation from the norm, progress is not possible.