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In-Reply-To: <20261026082730.2117173-1-zhanxusheng1024@gmail.com> References: <20261026082730.2117173-1-zhanxusheng1024@gmail.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: zhangqiao22@huawei.com, zhanxusheng1024@gmail.com, tglx@linutronix.de, jstultz@google.com, sboyd@kernel.org, peterz@infradead.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, zhanxusheng@xiaomi.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 26 Oct 2026 08:27:30 +0000, Zhan Xusheng wrote: > > On arm64 the system counter is meant to give all PEs a common view of > time, and keeping the copies on separate dies in step is the > implementation's job. The kernel has no tolerance for skew. The counter > errata handled in arm_arch_timer.c (Freescale A-008585, HiSilicon > 161010101, Cortex-A73 858921, Allwinner A64) are all reads on a single > CPU returning a wrong value, worked around by reading twice; none of them > is skew between CPUs. Indeed. If the implementation cannot give any two arbitrary CPUs anywhere in the system the exact same view of the counter, then this implementation is broken, and unsupported. No discussion. M. -- Without deviation from the norm, progress is not possible.