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Tue, 02 Aug 2022 00:14:10 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id z19-20020a2ebe13000000b0025e2b567434sm1801513ljq.9.2022.08.02.00.14.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Aug 2022 00:14:09 -0700 (PDT) Message-ID: <8715e07f-9d58-1ae3-9a3a-25828b545905@linaro.org> Date: Tue, 2 Aug 2022 10:14:09 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v3 5/8] drm/msm/a6xx: Ensure CX collapse during gpu recovery Content-Language: en-GB To: Akhil P Oommen , freedreno , dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , Bjorn Andersson Cc: Jordan Crouse , Jonathan Marek , Douglas Anderson , Matthias Kaehlcke , Abhinav Kumar , Chia-I Wu , Daniel Vetter , David Airlie , Philipp Zabel , Sean Paul , Stephen Boyd , linux-kernel@vger.kernel.org References: <1659174051-27816-1-git-send-email-quic_akhilpo@quicinc.com> <20220730150952.v3.5.I176567525af2b9439a7e485d0ca130528666a55c@changeid> From: Dmitry Baryshkov In-Reply-To: <20220730150952.v3.5.I176567525af2b9439a7e485d0ca130528666a55c@changeid> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30/07/2022 12:40, Akhil P Oommen wrote: > Because there could be transient votes from other drivers/tz/hyp which > may keep the cx gdsc enabled, we should poll until cx gdsc collapses. > We can use the reset framework to poll for cx gdsc collapse from gpucc > clk driver. > > This feature requires support from the platform's gpucc driver. > > Signed-off-by: Akhil P Oommen > --- > > Changes in v3: > - Use reset interface from gpucc driver to poll for cx gdsc collapse > https://patchwork.freedesktop.org/series/106860/ > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++++ > drivers/gpu/drm/msm/msm_gpu.c | 4 ++++ > drivers/gpu/drm/msm/msm_gpu.h | 4 ++++ > 3 files changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 1b049c5..721d5e6 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -10,6 +10,7 @@ > > #include > #include > +#include > #include > > #define GPU_PAS_ID 13 > @@ -1224,6 +1225,9 @@ static void a6xx_recover(struct msm_gpu *gpu) > /* And the final one from recover worker */ > pm_runtime_put_sync(&gpu->pdev->dev); > > + /* Call into gpucc driver to poll for cx gdsc collapse */ > + reset_control_reset(gpu->cx_collapse); Do we have a race between the last pm_runtime_put_sync(), this polling and other voters removing their votes beforehand? > + > pm_runtime_use_autosuspend(&gpu->pdev->dev); > > if (active_submits) > diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c > index 07e55a6..4a57627 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.c > +++ b/drivers/gpu/drm/msm/msm_gpu.c > @@ -14,6 +14,7 @@ > #include > #include > #include > +#include > #include > > /* > @@ -903,6 +904,9 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, > if (IS_ERR(gpu->gpu_cx)) > gpu->gpu_cx = NULL; > > + gpu->cx_collapse = devm_reset_control_get_optional(&pdev->dev, > + "cx_collapse"); > + > gpu->pdev = pdev; > platform_set_drvdata(pdev, &gpu->adreno_smmu); > > diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h > index 6def008..ab59fd2 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.h > +++ b/drivers/gpu/drm/msm/msm_gpu.h > @@ -13,6 +13,7 @@ > #include > #include > #include > +#include > > #include "msm_drv.h" > #include "msm_fence.h" > @@ -268,6 +269,9 @@ struct msm_gpu { > bool hw_apriv; > > struct thermal_cooling_device *cooling; > + > + /* To poll for cx gdsc collapse during gpu recovery */ > + struct reset_control *cx_collapse; > }; > > static inline struct msm_gpu *dev_to_gpu(struct device *dev) -- With best wishes Dmitry