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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id i27-20020a0565123e1b00b00507d219596dsm465396lfv.268.2023.11.07.13.49.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Nov 2023 13:49:03 -0800 (PST) Message-ID: <871e668a-1732-4ed6-9d12-818504296464@linaro.org> Date: Tue, 7 Nov 2023 22:48:59 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/6] media: qcom: camss: Add sc8280xp resource details Content-Language: en-US To: Bryan O'Donoghue , hverkuil-cisco@xs4all.nl, laurent.pinchart@ideasonboard.com, Andy Gross , Bjorn Andersson , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , vincent.knecht@mailoo.org, matti.lehtimaki@gmail.com, quic_grosikop@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20231105-b4-camss-sc8280xp-v3-0-4b3c372ff0f4@linaro.org> <20231105-b4-camss-sc8280xp-v3-4-4b3c372ff0f4@linaro.org> From: Konrad Dybcio In-Reply-To: <20231105-b4-camss-sc8280xp-v3-4-4b3c372ff0f4@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/5/23 18:45, Bryan O'Donoghue wrote: > This commit describes the hardware layout for the sc8280xp for the > following hardware blocks: > > - 4 x VFE, 4 RDI per VFE > - 4 x VFE Lite, 4 RDI per VFE > - 4 x CSID > - 4 x CSID Lite > - 4 x CSI PHY > > Signed-off-by: Bryan O'Donoghue > --- > drivers/media/platform/qcom/camss/camss.c | 383 ++++++++++++++++++++++++++++++ > 1 file changed, 383 insertions(+) > > diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c > index 8778fdc1ee342..51619842f3925 100644 > --- a/drivers/media/platform/qcom/camss/camss.c > +++ b/drivers/media/platform/qcom/camss/camss.c > @@ -941,6 +941,374 @@ static const struct resources_icc icc_res_sm8250[] = { > }, > }; > > +static const struct camss_subdev_resources csiphy_res_sc8280xp[] = { > + /* CSIPHY0 */ > + { > + .regulators = {}, > + .clock = { "csiphy0", "csiphy0_timer" }, > + .clock_rate = { { 400000000 }, > + { 300000000 } }, > + .reg = { "csiphy0" }, > + .interrupt = { "csiphy0" }, > + .ops = &csiphy_ops_3ph_1_0 > + }, > + /* CSIPHY1 */ > + { > + .regulators = {}, > + .clock = { "csiphy1", "csiphy1_timer" }, > + .clock_rate = { { 400000000 }, > + { 300000000 } }, > + .reg = { "csiphy1" }, > + .interrupt = { "csiphy1" }, > + .ops = &csiphy_ops_3ph_1_0 > + }, > + /* CSIPHY2 */ > + { > + .regulators = {}, > + .clock = { "csiphy2", "csiphy2_timer" }, > + .clock_rate = { { 400000000 }, > + { 300000000 } }, > + .reg = { "csiphy2" }, > + .interrupt = { "csiphy2" }, > + .ops = &csiphy_ops_3ph_1_0 > + }, > + /* CSIPHY3 */ > + { > + .regulators = {}, > + .clock = { "csiphy3", "csiphy3_timer" }, > + .clock_rate = { { 400000000 }, > + { 300000000 } }, > + .reg = { "csiphy3" }, > + .interrupt = { "csiphy3" }, > + .ops = &csiphy_ops_3ph_1_0 > + }, > +}; > + > +static const struct camss_subdev_resources csid_res_sc8280xp[] = { > + /* CSID0 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + .clock = { "vfe0_csid_src", "vfe0_csid", "cphy_rx_src", > + "vfe0_cphy_rx", "vfe0_src", "vfe0", "vfe0_axi" }, This looks like downstream hack copypasta.. All the _src clocks should be axed from here, from the camss bindings and simply be enabled with CLK_OPS_PARENT_ENABLE on their children (which should be the default for all branch clocks anyway eh) Konrad