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Mon, 31 Aug 2026 23:31:58 -0700 (PDT) X-Received: by 2002:a17:90a:da83:b0:38f:efed:5445 with SMTP id 98e67ed59e1d1-396d0de796fmr49247516a91.4.1788244317572; Mon, 31 Aug 2026 23:31:57 -0700 (PDT) Received: from [10.217.216.70] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3286f9e2a95sm34010711eec.23.2026.08.31.23.31.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 31 Aug 2026 23:31:57 -0700 (PDT) Message-ID: <87244cbb-53b4-4deb-bf91-d5570879db09@oss.qualcomm.com> Date: Tue, 1 Sep 2026 12:01:50 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Imran Shaik Subject: Re: [PATCH 2/6] dt-bindings: ptp: Document TSCSS hardware on Qualcomm QDU1000 SoC To: Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bjorn Andersson , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org References: <20260727-tscss-v1-0-beed14e72510@oss.qualcomm.com> <20260727-tscss-v1-2-beed14e72510@oss.qualcomm.com> <184d7977-891b-4d18-983f-7d23a7d9ff83@kernel.org> Content-Language: en-US In-Reply-To: <184d7977-891b-4d18-983f-7d23a7d9ff83@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=b9qCJNGx c=1 sm=1 tr=0 ts=6a96715f cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VFrjYgP8P-MpaLTDB6EA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDA1NyBTYWx0ZWRfXwXIuPvmr5ST/ o8+86N4l6o69AU8SmOuninarDBOp9CEn74/gH20MSolhvpD8mafZYTHg8d95udy8ERRi7Po9P1S LBpuoy1+676U63lGj4T+FstkHn31HPclAt9bkPk3wDKZbcEKnKWKgsyK9B8A17AIHaJZwhuGA1z VHWf8plbE4G88kaIcBMmlWe1+BTadr/q+ukbYw7gALsN3X3sX9//rhk1XEe4jRzcLALrhFW57zt BodBCcJHJrxh3vZ8pAIUWo6uGkCjX0FgZ612Kdh+o4tK+h/WxmtH9ssjVC/ob6sBNzHitOdh1nL KNKga9kfXsBrKPZjxBBEf3nqePhSTurH5pETW3TINAshD3sSwlGyGxC9NRGHaOwDZFWXSbSXkIh p2VRBMoSAj6gvh0csmEr9MNlJsyNnx8WKkh41tDoOlYZWij6sYGRfRIdSqxwFJ0kwNW3xB+VyNw MhTPqpqydr32Fz5mMmA== X-Proofpoint-GUID: V59FxxeYWfmDsU5Bx64xO0pyhIaLnRTj X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDA1NyBTYWx0ZWRfX7+lHNcgB8rV9 kAaJuwuDMSZ7+Um8m/3ox7qJcgXYxPuCOgBfxWGXug6e6SQE2FbJUI5nEMGkvDOlhEUlZNoEFA/ OdZ7JuILWuWiST2jOd5QIcqz25RI42Q= X-Proofpoint-ORIG-GUID: V59FxxeYWfmDsU5Bx64xO0pyhIaLnRTj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_01,2026-08-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 phishscore=0 clxscore=1015 impostorscore=0 spamscore=0 priorityscore=1501 adultscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010057 On 27-07-2026 09:21 pm, Krzysztof Kozlowski wrote: > On 27/07/2026 16:10, Imran Shaik wrote: >> Add Devicetree bindings for the Timestamp Counter Subsystem (TSCSS) found >> on Qualcomm QDU1000 SoC. >> >> TSCSS is a time synchronization subsystem composed of two main blocks: >> Timestamp Counter (TSC) and Event Timestamp Unit (ETU). The TSC block >> provides a continuously running counter used for timekeeping, while the >> ETU captures timestamps for external hardware event triggers. >> >> Co-developed-by: Taniya Das >> Signed-off-by: Taniya Das >> Signed-off-by: Imran Shaik >> --- >> .../bindings/ptp/qcom,qdu1000-tscss.yaml | 187 +++++++++++++++++++++ >> 1 file changed, 187 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/ptp/qcom,qdu1000-tscss.yaml b/Documentation/devicetree/bindings/ptp/qcom,qdu1000-tscss.yaml >> new file mode 100644 >> index 0000000000000000000000000000000000000000..39387614ef8939b7840df2f0d5640b9e142fb4e5 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/ptp/qcom,qdu1000-tscss.yaml >> @@ -0,0 +1,187 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/ptp/qcom,qdu1000-tscss.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Timestamp Counter Subsystem (TSCSS) on Qualcomm QDU1000 SoC >> + >> +maintainers: >> + - Imran Shaik >> + - Taniya Das >> + >> +description: | >> + Qualcomm TSCSS is a time synchronization subsystem composed of two main >> + blocks - the Time Stamp Counter (TSC) and the Event Timestamp Unit (ETU). >> + >> + The TSC block is a timestamp generator that maintains a running counter used >> + for system timekeeping, and is functional with just the AHB and counter >> + clocks. >> + The ETU block is optional and captures TSC timestamps for external >> + hardware events, each ETU slice binding a slice identifier to an external >> + event selector. Support for the ETU block requires the additional ETU >> + clock along with the per slice interrupt and slice subnodes. >> + >> +properties: >> + compatible: >> + const: qcom,qdu1000-tscss > > Why do you create a new file with exactly the same binding? > The QDU1000 SoC TSCSS has the per ETU slice IRQ lines. Where as in Lemans/Monaco, it is summary IRQ line for all the ETU slices. Hence, kept two different bindings for both the SoCs. > Anyway, all comments apply. > Sure, will take care of those comments here as well. Thanks, Imran