From: Chenyi Qiang <chenyi.qiang@intel.com>
To: Sean Christopherson <seanjc@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
Xiaoyao Li <xiaoyao.li@intel.com>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 5/7] KVM: MMU: Add support for PKS emulation
Date: Thu, 31 Mar 2022 13:43:51 +0800 [thread overview]
Message-ID: <873f6789-6ec2-245c-d61d-98a14b546733@intel.com> (raw)
In-Reply-To: <YkTLXGdu2I9i44ti@google.com>
On 3/31/2022 5:27 AM, Sean Christopherson wrote:
> On Mon, Feb 21, 2022, Chenyi Qiang wrote:
>> @@ -277,14 +278,18 @@ static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
>> WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
>> if (unlikely(mmu->pkr_mask)) {
>> u32 pkr_bits, offset;
>> + u32 pkr;
>>
>> /*
>> - * PKRU defines 32 bits, there are 16 domains and 2
>> - * attribute bits per domain in pkru. pte_pkey is the
>> - * index of the protection domain, so pte_pkey * 2 is
>> - * is the index of the first bit for the domain.
>> + * PKRU and PKRS both define 32 bits. There are 16 domains
>> + * and 2 attribute bits per domain in them. pte_key is the
>> + * index of the protection domain, so pte_pkey * 2 is the
>> + * index of the first bit for the domain. The use of PKRU
>> + * versus PKRS is selected by the address type, as determined
>> + * by the U/S bit in the paging-structure entries.
>> */
>> - pkr_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
>> + pkr = pte_access & PT_USER_MASK ? vcpu->arch.pkru : kvm_read_pkrs(vcpu);
>
> Blindly reading PKRU/PKRS is wrong. I think this magic insanity will be functionally
> correct due to update_pkr_bitmask() clearing the appropriate bits in pkr_mask based
> on CR4.PK*, but the read should never happen. PKRU is benign, but I believe reading
> PKRS will result in VMREAD to an invalid field if PKRU is supported and enabled, but
> PKRS is not supported.
>
Nice catch.
> I belive the easiest solution is:
>
> if (pte_access & PT_USER_MASK)
> pkr = is_cr4_pke(mmu) ? vcpu->arch.pkru : 0;
> else
> pkr = is_cr4_pks(mmu) ? kvm_read_pkrs(vcpu) : 0;
>
> The is_cr4_pk*() helpers are restricted to mmu.c, but this presents a good
> opportunity to extra the PKR stuff to a separate, non-inline helper (as a prep
> patch). E.g.
>
>
> WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
> if (unlikely(mmu->pkr_mask))
> u32 pkr_bits = kvm_mmu_pkr_bits(vcpu, mmu, pte_access, pte_pkey);
>
> errcode |= -pkr_bits & PFERR_PK_MASK;
> fault |= (pkr_bits != 0);
> }
>
> return -(u32)fault & errcode;
>
> permission_fault() is inline because it's heavily used for shadow paging, but
> when using TDP, it's far less performance critical. PKR is TDP-only, so moving
> it out-of-line should be totally ok (this is also why this patch is "unlikely").
Make sense, will do it.
next prev parent reply other threads:[~2022-03-31 5:44 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-21 8:08 [PATCH v6 0/7] KVM: PKS Virtualization support Chenyi Qiang
2022-02-21 8:08 ` [PATCH v6 1/7] KVM: VMX: Introduce PKS VMCS fields Chenyi Qiang
2022-03-30 20:05 ` Sean Christopherson
2022-02-21 8:08 ` [PATCH v6 2/7] KVM: VMX: Add proper cache tracking for PKRS Chenyi Qiang
2022-03-30 20:42 ` Sean Christopherson
2022-03-31 5:39 ` Chenyi Qiang
2022-02-21 8:08 ` [PATCH v6 3/7] KVM: X86: Expose IA32_PKRS MSR Chenyi Qiang
2022-02-21 8:08 ` [PATCH v6 4/7] KVM: MMU: Rename the pkru to pkr Chenyi Qiang
2022-02-21 8:08 ` [PATCH v6 5/7] KVM: MMU: Add support for PKS emulation Chenyi Qiang
2022-03-30 21:27 ` Sean Christopherson
2022-03-31 5:43 ` Chenyi Qiang [this message]
2022-02-21 8:08 ` [PATCH v6 6/7] KVM: VMX: Expose PKS to guest Chenyi Qiang
2022-03-30 21:30 ` Sean Christopherson
2022-02-21 8:08 ` [PATCH v6 7/7] KVM: VMX: Enable PKS for nested VM Chenyi Qiang
2022-03-30 21:47 ` Sean Christopherson
2022-03-31 6:08 ` Chenyi Qiang
2022-03-07 6:09 ` [PATCH v6 0/7] KVM: PKS Virtualization support Chenyi Qiang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=873f6789-6ec2-245c-d61d-98a14b546733@intel.com \
--to=chenyi.qiang@intel.com \
--cc=jmattson@google.com \
--cc=joro@8bytes.org \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=pbonzini@redhat.com \
--cc=seanjc@google.com \
--cc=vkuznets@redhat.com \
--cc=wanpengli@tencent.com \
--cc=xiaoyao.li@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®