From: NeilBrown <neil@brown.name>
To: Matt Redfearn <matt.redfearn@mips.com>,
John Crispin <john@phrozen.org>,
Ralf Baechle <ralf@linux-mips.org>,
James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] MIPS: ralink: fix booting on mt7621
Date: Wed, 21 Mar 2018 14:00:44 +1100 [thread overview]
Message-ID: <874lla874z.fsf@notabene.neil.brown.name> (raw)
In-Reply-To: <cc33f000-16ed-b331-53b7-d767e20a4a9c@mips.com>
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On Tue, Mar 20 2018, Matt Redfearn wrote:
> Hi Neil,
>
>
> On 20/03/18 08:22, NeilBrown wrote:
>>
>> Further testing showed that the original version of this
>> patch wasn't 100% reliable. Very occasionally the read
>> of SYSC_REG_CHIP_NAME0 returns garbage. Repeating the
>> read seems to be reliable, but it hasn't happened enough
>> for me to be completely confident.
>> So this version repeats that first read.
>
> You almost certainly need a sync() to ensure that the write to gcr_reg0
> has completed before attempting to read sysc + SYSC_REG_CHIP_NAME0.
That sound like exactly the right sort of thing to do, though
I assume you mean __sync().
I tried to reproduce the problem so I could test the fix, and of course
I failed. Over 700 reboot cycles and never read any garbage from
SYSC_REG_CHIP_NAME0.
So I cannot test that this works, but I have tested that it doesn't
cause any obvious regression.
I'll send the v3 patch separately.
Thanks a lot,
NeilBrown
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next prev parent reply other threads:[~2018-03-21 3:00 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-20 4:00 [PATCH] " NeilBrown
2018-03-20 8:22 ` [PATCH v2] " NeilBrown
2018-03-20 11:01 ` Matt Redfearn
2018-03-21 3:00 ` NeilBrown [this message]
2018-03-21 8:51 ` Matt Redfearn
2018-03-21 3:02 ` [PATCH v3] " NeilBrown
2018-03-21 8:52 ` Matt Redfearn
2018-03-22 0:11 ` James Hogan
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