From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752063AbcDRGjm (ORCPT ); Mon, 18 Apr 2016 02:39:42 -0400 Received: from mail1.asahi-net.or.jp ([202.224.39.197]:18866 "EHLO mail1.asahi-net.or.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751223AbcDRGjl (ORCPT ); Mon, 18 Apr 2016 02:39:41 -0400 Date: Mon, 18 Apr 2016 15:39:38 +0900 Message-ID: <874mazcted.wl-ysato@users.sourceforge.jp> From: Yoshinori Sato To: Stephen Boyd Cc: Michael Turquette , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] clk: Add 16bit register access for clk-divider. In-Reply-To: <20160416000635.GB26353@codeaurora.org> References: <1460618263-30967-1-git-send-email-ysato@users.sourceforge.jp> <20160416000635.GB26353@codeaurora.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL/10.8 EasyPG/1.0.0 Emacs/24.5 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 16 Apr 2016 09:06:35 +0900, Stephen Boyd wrote: > > On 04/14, Yoshinori Sato wrote: > > Some SoC use 16bit-word register. And required 16bit-word access. > > This changes add 16-bit access mode. > > > > Signed-off-by: Yoshinori Sato > > Please implement a custom divider for your hardware instead of > adding this support to the core. You can call functions such as > divider_recalc_rate(), divider_round_rate(), and > divider_get_val() to get the appropriate register values and then > have the readw/writew in your custom driver instead. OK. > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project -- Yoshinori Sato