From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756494AbbI1HLK (ORCPT ); Mon, 28 Sep 2015 03:11:10 -0400 Received: from mga03.intel.com ([134.134.136.65]:13454 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756367AbbI1HLI (ORCPT ); Mon, 28 Sep 2015 03:11:08 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,602,1437462000"; d="scan'208";a="814296406" From: Jani Nikula To: Brian Norris , intel-gfx@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org, Brian Norris , Daniel Vetter , Rodrigo Vivi , =?utf-8?Q?St=C3=A9phane?= Marchesin , Duncan Laurie , Brian Norris Subject: Re: [RFC PATCH] drm/i915: PSR regressions on Broadwell In-Reply-To: <1443234373-107752-1-git-send-email-briannorris@chromium.org> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <1443234373-107752-1-git-send-email-briannorris@chromium.org> User-Agent: Notmuch/0.20.2+58~g39779b9 (http://notmuchmail.org) Emacs/24.4.1 (x86_64-pc-linux-gnu) Date: Mon, 28 Sep 2015 10:14:04 +0300 Message-ID: <874mifm2wz.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 26 Sep 2015, Brian Norris wrote: > When using PSR, I see the screen freeze after only a few frames (sometimes a > split second; sometimes it seems like practically the first frame). Bisecting > led me to commit 3301d4092106 ("drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT > logic") in v4.2. This patch is the simplest fix that gets it working again for > me, but it's probably wrong. > > Random thought: perhaps my panel's DPCD is programmed incorrectly? > > Anyway, any tips on fixing this properly? Here's a thought: diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index a04b4dc5ed9b..3a911d4a2308 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -274,6 +274,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) idle_frames += 4; } + idle_frames = clamp(idle_frames, 0, 15); + I915_WRITE(EDP_PSR_CTL(dev), val | (IS_BROADWELL(dev) ? 0 : link_entry_time) | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | We do clamp the VBT value to range 0..15, but then go on to add to it. Otherwise, up to Rodrigo I guess. BR, Jani. > > Seen on Chromebook Pixel 2. > > Also required this patch to get PSR properly running on 4.3-rc2: > > https://patchwork.freedesktop.org/patch/57698/ > > Signed-off-by: Brian Norris > --- > drivers/gpu/drm/i915/intel_psr.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index 7e335a8546f6..4cd33b76b8a6 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -261,7 +261,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) > uint32_t val = 0x0; > const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; > > - if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { > + if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) && > + !IS_BROADWELL(dev)) { > /* It doesn't mean we shouldn't send TPS patters, so let's > send the minimal TP1 possible and skip TP2. */ > val |= EDP_PSR_TP1_TIME_100us; > -- > 2.6.0.rc2.230.g3dd15c0 > -- Jani Nikula, Intel Open Source Technology Center