From: John Garry <john.garry@huawei.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Zhou Wang <wangzhou1@hisilicon.com>,
<linux-kernel@vger.kernel.org>,
"luojiaxing@huawei.com" <luojiaxing@huawei.com>
Subject: Re: PCI MSI issue with reinserting a driver
Date: Tue, 6 Apr 2021 10:46:28 +0100 [thread overview]
Message-ID: <87547f6c-2f50-7a91-c629-bbfe7c22a49b@huawei.com> (raw)
In-Reply-To: <3d3d0155e66429968cb4f6b4feeae4b3@kernel.org>
On 03/02/2021 17:23, Marc Zyngier wrote:
> On 2021-02-02 15:46, John Garry wrote:
>> On 02/02/2021 14:48, Marc Zyngier wrote:
>>>>>
>>>>> Not sure. I also now notice an error for the SAS PCI driver on D06
>>>>> when nr_cpus < 16, which means number of MSI vectors allocated <
>>>>> 32, so looks the same problem. There we try to allocate 16 + max(nr
>>>>> cpus, 16) MSI.
>>>>>
>>>>> Anyway, let me have a look today to see what is going wrong.
>>>>>
>>>> Could this be the problem:
>>>>
>>>> nr_cpus=11
>>>>
>>>> In alloc path, we have:
>>>> its_alloc_device_irq(nvecs=27 = 16+11)
>>>> bitmap_find_free_region(order = 5);
>>>> In free path, we have:
>>>> its_irq_domain_free(nvecs = 1) and free each 27 vecs
>>>> bitmap_release_region(order = 0)
>>>>
>>>> So we allocate 32 bits, but only free 27. And 2nd alloc for 32 fails.
>>
>> [ ... ]
>>
>>>>
Hi Marc,
Just a friendly reminder on this issue. Let me know if anything required
some our side.
Cheers,
John
>>>>
>>>> But I'm not sure that we have any requirement for those map bits to be
>>>> consecutive.
>>>
>>> We can't really do that. All the events must be contiguous,
>>> and there is also a lot of assumptions in the ITS driver that
>>> LPI allocations is also contiguous.
>>>
>>> But there is also the fact that for Multi-MSI, we *must*
>>> allocate 32 vectors. Any driver could assume that if we have
>>> allocated 17 vectors, then there is another 15 available.
>>>
>>> My question still stand: how was this working with the previous
>>> behaviour?
>>
>> Because previously in this scenario we would allocate 32 bits and free
>> 32 bits in the map; but now we allocate 32 bits, yet only free 27 - so
>> leak 5 bits. And this comes from how irq_domain_free_irqs_hierarchy()
>> now frees per-interrupt, instead of all irqs per domain.
>>
>> Before:
>> In free path, we have:
>> its_irq_domain_free(nvecs = 27)
>> bitmap_release_region(count order = 5 == 32bits)
>>
>> Current:
>> In free path, we have:
>> its_irq_domain_free(nvecs = 1) for free each 27 vecs
>> bitmap_release_region(count order = 0 == 1bit)
>
> Right. I was focusing on the patch and blindly ignored the explanation
> at the top of the email. Apologies for that.
>
> I'm not overly keen on handling this in the ITS though, and I'd rather
> we try and do it in the generic code. How about this (compile tested
> only)?
>
> Thanks,
>
> M.
>
> diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
> index 6aacd342cd14..cfccad83c2df 100644
> --- a/kernel/irq/irqdomain.c
> +++ b/kernel/irq/irqdomain.c
> @@ -1399,8 +1399,19 @@ static void irq_domain_free_irqs_hierarchy(struct
> irq_domain *domain,
> return;
>
> for (i = 0; i < nr_irqs; i++) {
> - if (irq_domain_get_irq_data(domain, irq_base + i))
> - domain->ops->free(domain, irq_base + i, 1);
> + int n ;
> +
> + /* Find the largest possible span of IRQs to free in one go */
> + for (n = 0;
> + ((i + n) < nr_irqs &&
> + irq_domain_get_irq_data(domain, irq_base + i + n));
> + n++);
> +
> + if (!n)
> + continue;
> +
> + domain->ops->free(domain, irq_base + i, n);
> + i += n;
> }
> }
>
>
next prev parent reply other threads:[~2021-04-06 9:49 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-01 18:34 John Garry
2021-02-01 18:50 ` Marc Zyngier
2021-02-02 8:37 ` John Garry
2021-02-02 12:38 ` John Garry
2021-02-02 14:48 ` Marc Zyngier
2021-02-02 15:46 ` John Garry
2021-02-03 17:23 ` Marc Zyngier
2021-02-04 10:45 ` John Garry
2022-08-04 10:59 ` John Garry
2021-04-06 9:46 ` John Garry [this message]
2021-08-27 8:33 ` luojiaxing
2023-08-29 23:00 ` Thomas Gleixner
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