From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22ED5ECDFB3 for ; Tue, 17 Jul 2018 10:29:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D9ED920C0A for ; Tue, 17 Jul 2018 10:29:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D9ED920C0A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730638AbeGQLBD (ORCPT ); Tue, 17 Jul 2018 07:01:03 -0400 Received: from mga09.intel.com ([134.134.136.24]:36971 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729718AbeGQLBD (ORCPT ); Tue, 17 Jul 2018 07:01:03 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Jul 2018 03:28:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,365,1526367600"; d="scan'208";a="73015709" Received: from ahunter-desktop.fi.intel.com (HELO [10.237.72.168]) ([10.237.72.168]) by fmsmga001.fm.intel.com with ESMTP; 17 Jul 2018 03:28:33 -0700 Subject: Re: [PATCH] mmc: tegra: Force correct divider calculation on DDR50/52 To: Aapo Vienamo , Ulf Hansson , Thierry Reding , Jonathan Hunter , Marcel Ziswiler , Stefan Agner Cc: linux-mmc@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <1531751669-26584-1-git-send-email-avienamo@nvidia.com> From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Message-ID: <875ad3f9-81b9-2c50-be1d-4550fd9e3b44@intel.com> Date: Tue, 17 Jul 2018 13:26:58 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.0 MIME-Version: 1.0 In-Reply-To: <1531751669-26584-1-git-send-email-avienamo@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16/07/18 17:34, Aapo Vienamo wrote: > Tegra SDHCI controllers require the SDHCI clock divider to be configured > to divide the clock by two in DDR50/52 modes. Incorrectly configured > clock divider results in corrupted data. > > Prevent the possibility of incorrectly calculating the divider value due > to clock rate rounding or low parent clock frequency by not assigning > host->max_clk to clk_get_rate() on tegra_sdhci_set_clock(). > > See the comments for further details. > > Fixes: a8e326a ("mmc: tegra: implement module external clock change") > Signed-off-by: Aapo Vienamo Acked-by: Adrian Hunter > --- > drivers/mmc/host/sdhci-tegra.c | 17 ++++++++++++++++- > 1 file changed, 16 insertions(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c > index ddf00166..908b23e 100644 > --- a/drivers/mmc/host/sdhci-tegra.c > +++ b/drivers/mmc/host/sdhci-tegra.c > @@ -210,9 +210,24 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) > if (!clock) > return sdhci_set_clock(host, clock); > > + /* > + * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI > + * divider to be configured to divided the host clock by two. The SDHCI > + * clock divider is calculated as part of sdhci_set_clock() by > + * sdhci_calc_clk(). The divider is calculated from host->max_clk and > + * the requested clock rate. > + * > + * By setting the host->max_clk to clock * 2 the divider calculation > + * will always result in the correct value for DDR50/52 modes, > + * regardless of clock rate rounding, which may happen if the value > + * from clk_get_rate() is used. > + */ > host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; > clk_set_rate(pltfm_host->clk, host_clk); > - host->max_clk = clk_get_rate(pltfm_host->clk); > + if (tegra_host->ddr_signaling) > + host->max_clk = host_clk; > + else > + host->max_clk = clk_get_rate(pltfm_host->clk); > > sdhci_set_clock(host, clock); > >