From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2570C3E3166 for ; Mon, 10 Aug 2026 14:06:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786370774; cv=none; b=nE/hs+Lyhr65RagTdfmGhSq2tKbhWSRx5oBOr9qmMATal9QXet+CsynrA2pladrcGdYTEFrRGaPRY5vDz1Hofz5H9RTxqOBie/jAY1J8WiJk4iiQXmyekjiQrVPrBBVy4St2Jrq/SrR5JcvytFw2yuAPmBGURYSw41RoLW6mh0g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786370774; c=relaxed/simple; bh=CvM3MTmlrFxN3QrG/GnOK9O/WjcLd399D+a1DSfnP44=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=VLsgZX1YaYRTb1RtqsjEQtF64VXCgjIQl4FxvW/y3z3HcKhPGDXrWtVTZ9GoKm3+BL3BiispWak4lOABtoMQ4Ay4SBKzaEaiogMH0HRe70O3hHnugogrPNfVHwpaVg3eIBI6d7S6VUSlK5TuzN8GLJG2Qg85FjaWyRM8wZrPaAI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=sOj3nodO; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="sOj3nodO" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 394354E411A7; Mon, 10 Aug 2026 14:06:09 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 04E596033B; Mon, 10 Aug 2026 14:06:09 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id EF18F11C4A82D; Mon, 10 Aug 2026 16:05:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1786370768; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=CvM3MTmlrFxN3QrG/GnOK9O/WjcLd399D+a1DSfnP44=; b=sOj3nodO6jx41/2DNx2k4PciPwaiWzQV9MwLm1ov+xDgDV1DNDjN66VbS6IReNs6nrXycZ hgj71e3rCeJTMAaaIoCHTgjMYH+Jt++u/eWRWlswU2SlpnylYQ3IGJagrRGLpmsHJLBphv VlyMrkiwL9vuX001v2/SCfGZ71zxLsqD09o++95HNiK3bZc2UGhkgoRLsELcX17ATxr3DX uFQwVc3nMa3oLx3KbhFeIXhHQMLlGu5rEgS9yqJ/01HiZ2TkFZtybkqsZX/2NT9FXI2jYZ DO1pFXFkiUI3lH0XSyMhxdWBvx4JX9jAOa2latSKIuF2l3IYqy95rUAHF2yeRg== From: Miquel Raynal To: "Michael Walle" Cc: "Pratyush Yadav" , "Takahiro Kuwano" , "Richard Weinberger" , "Vignesh Raghavendra" , "Nicolas Ferre" , "Alexandre Belloni" , "Claudiu Beznea" , "Steam Lin" , "Hsin-Yi Wang" , "Thomas Petazzoni" , , , Subject: Re: [PATCH 1/5] mtd: spi-nor: Refactor Read Status/Write Status support In-Reply-To: (Michael Walle's message of "Mon, 10 Aug 2026 09:18:07 +0200") References: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com> <20260529-winbond-v7-1-spi-nor-rv-addition-v1-1-f3ae18502d5a@bootlin.com> <87mrv2exwp.fsf@bootlin.com> <87se4rem0l.fsf@bootlin.com> User-Agent: mu4e 1.12.12; emacs 30.2 Date: Mon, 10 Aug 2026 16:05:59 +0200 Message-ID: <875x1iqddk.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 On 10/08/2026 at 09:18:07 +02, "Michael Walle" wrote: > On Thu Aug 6, 2026 at 9:38 AM CEST, Miquel Raynal wrote: >> Hello Michael, >> >>>> One thing that comes to mind is hardware write protection. If >>>> there's nothing before that code which checks it, the verify might >>>> fail if the hardware write protection is enabled. So we should >>>> somehow check for that and drop the verify here. >>> >>> But how do you think we should handle it? Will the QE bit writing >>> verification fail if HW WP is enabled? > > It should, because you cannot alter the SR. > >> Looking into this further: we shall return an error if the QE bit is not >> set. It just tells the caller that quad mode cannot be used. Then up to >> the caller to either hard fail or just degrade into single mode (maybe >> because of a strapped WP). What we should do is to propose a DT property >> to flag when WP is strapped in hardware, this would make the content of >> the status registers immutable and we would just skip the entire write >> operation in the first place, instead of deliberately trying and get a >> 100% failure rate. Nevertheless, the changes introduced here are kind of >> orthogonal and do not alter the current behaviour; we shall however >> listen if people start complaining about this and perhaps implement the >> solution proposed above. > > There is already a property in the DT, where you almost certainly > know that quad mode is impossible. Iff there are four rx/tx lines > (spi-{rx,tx}-bus-width). I haven't seen a flash (even in larger > packages) where there is a dedicated WP# pin. > > What do you mean by a dt property? If (1) the flash is using the WP# > pin? Or (2) if it is using the WP# pin and it's tied to low? > > For (1) you have the QE bit, if it's set, WP is turned off and vice > versa. > > For (2), that doesn't make sense, because that pin could be tied > to some kind of logic which can change during runtime. > > FWIW, I don't care too much, you've asked why there is a > verification step, I've just answered :) Thank you :) Anyway, I've reinstated these checks in my last version. If you look at it, don't focus on the commit about the names, I need to fix that up again by adding some kind of "hide" flag for the RV chips, instead of dropping the names (the rest won't change much). Thanks, Miqu=C3=A8l