From: Jon Hunter <jonathanh@nvidia.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Ashish Mhetre <amhetre@nvidia.com>,
robh+dt@kernel.org, thierry.reding@gmail.com, digetx@gmail.com,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org
Cc: vdumpa@nvidia.com, Snikam@nvidia.com
Subject: Re: [Patch v4 3/4] memory: tegra: Add memory controller channels support
Date: Wed, 9 Mar 2022 08:56:01 +0000 [thread overview]
Message-ID: <876010c1-0558-bd1e-e133-05403e5a167b@nvidia.com> (raw)
In-Reply-To: <34646ebd-2c37-65ec-ecfe-cfbfa4bd29d2@canonical.com>
On 02/03/2022 19:35, Krzysztof Kozlowski wrote:
> On 02/03/2022 09:43, Ashish Mhetre wrote:
>> From tegra186 onwards, memory controller support multiple channels.
>> Add support for mapping address spaces of these channels.
>> During error interrupts from memory controller, appropriate registers
>> from these channels need to be accessed for logging error info.
>>
>> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
>> ---
>> drivers/memory/tegra/mc.c | 6 ++++++
>> drivers/memory/tegra/tegra186.c | 21 +++++++++++++++++++++
>> drivers/memory/tegra/tegra194.c | 1 +
>> drivers/memory/tegra/tegra234.c | 1 +
>> include/soc/tegra/mc.h | 7 +++++++
>> 5 files changed, 36 insertions(+)
>>
>> diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
>> index bf3abb6..3cda1d9 100644
>> --- a/drivers/memory/tegra/mc.c
>> +++ b/drivers/memory/tegra/mc.c
>> @@ -749,6 +749,12 @@ static int tegra_mc_probe(struct platform_device *pdev)
>> if (IS_ERR(mc->regs))
>> return PTR_ERR(mc->regs);
>>
>> + if (mc->soc->ops && mc->soc->ops->map_regs) {
>> + err = mc->soc->ops->map_regs(mc, pdev);
>> + if (err < 0)
>> + return err;
>> + }
>> +
>> mc->debugfs.root = debugfs_create_dir("mc", NULL);
>>
>> if (mc->soc->ops && mc->soc->ops->probe) {
>> diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
>> index 3d15388..59a4425 100644
>> --- a/drivers/memory/tegra/tegra186.c
>> +++ b/drivers/memory/tegra/tegra186.c
>> @@ -139,11 +139,31 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
>> return 0;
>> }
>>
>> +static int tegra186_mc_map_regs(struct tegra_mc *mc,
>> + struct platform_device *pdev)
>> +{
>> + struct resource *res;
>> + int i;
>> +
>> + mc->mcb_regs = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
>> + if (IS_ERR(mc->mcb_regs))
>> + return PTR_ERR(mc->mcb_regs);
>> +
>> + for (i = 0; i < mc->soc->num_channels; i++) {
>> + mc->mc_regs[i] = devm_platform_get_and_ioremap_resource(pdev, i + 2, &res);
>> + if (IS_ERR(mc->mc_regs[i]))
>> + return PTR_ERR(mc->mc_regs[i]);
>
> This breaks the ABI, so I need Thierry's ack that such ABI break is
> perfectly ok.
We should not break the DT ABI and so if all the reg entries it should
still be able to work.
Jon
--
nvpublic
next prev parent reply other threads:[~2022-03-09 8:56 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-02 8:43 [Patch v4 0/4] memory: tegra: Add MC channels and error logging Ashish Mhetre
2022-03-02 8:43 ` [Patch v4 1/4] arm64: tegra: Add memory controller channels Ashish Mhetre
2022-03-02 19:32 ` Krzysztof Kozlowski
2022-03-02 8:43 ` [Patch v4 2/4] dt-bindings: memory: Update reg maxitems for tegra186 Ashish Mhetre
2022-03-02 17:51 ` Rob Herring
2022-03-02 19:31 ` Krzysztof Kozlowski
2022-03-02 8:43 ` [Patch v4 3/4] memory: tegra: Add memory controller channels support Ashish Mhetre
2022-03-02 19:35 ` Krzysztof Kozlowski
2022-03-09 8:56 ` Jon Hunter [this message]
2022-03-02 8:43 ` [Patch v4 4/4] memory: tegra: Add MC error logging on tegra186 onward Ashish Mhetre
2022-03-02 19:44 ` Krzysztof Kozlowski
2022-03-07 19:02 ` Ashish Mhetre
2022-03-03 12:31 ` Dan Carpenter
2022-03-03 13:03 ` Krzysztof Kozlowski
2022-03-07 19:47 ` Ashish Mhetre
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