From: Thomas Gleixner <tglx@linutronix.de>
To: Kees Cook <keescook@chromium.org>
Cc: "Saripalli\, RK" <rsaripal@amd.com>,
linux-kernel@vger.kernel.org, x86@kernel.org, mingo@redhat.com,
bp@alien8.de, hpa@zytor.com, Jonathan Corbet <corbet@lwn.net>,
bsd@redhat.com, Josh Poimboeuf <jpoimboe@redhat.com>
Subject: Re: [PATCH v5 1/1] x86/cpufeatures: Implement Predictive Store Forwarding control.
Date: Tue, 11 May 2021 00:15:32 +0200 [thread overview]
Message-ID: <878s4mgrqz.ffs@nanos.tec.linutronix.de> (raw)
In-Reply-To: <202105101508.BC6CC99FAD@keescook>
On Mon, May 10 2021 at 15:09, Kees Cook wrote:
> On Mon, May 10, 2021 at 11:44:03PM +0200, Thomas Gleixner wrote:
>> Kees, any opinions?
>
> I agree: if PSF is a subset of SSBD, there's no need for the additional
> machinery.
>
> On a related topic, what happened to Andi's patch to switch the seccomp
> defaults? I can't find it now...
You mean this one:
https://lore.kernel.org/r/20200312231222.81861-1-andi@firstfloor.org
If so, then it has lacks a follow up.
Thanks,
tglx
next prev parent reply other threads:[~2021-05-10 22:15 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-05 19:09 [PATCH v5 0/1] Introduce support for PSF control Ramakrishna Saripalli
2021-05-05 19:09 ` [PATCH v5 1/1] x86/cpufeatures: Implement Predictive Store Forwarding control Ramakrishna Saripalli
2021-05-07 15:13 ` Thomas Gleixner
2021-05-07 15:23 ` Saripalli, RK
2021-05-07 15:33 ` Thomas Gleixner
2021-05-10 11:10 ` Saripalli, RK
2021-05-10 21:44 ` Thomas Gleixner
2021-05-10 22:01 ` Saripalli, RK
2021-05-10 22:09 ` Kees Cook
2021-05-10 22:15 ` Thomas Gleixner [this message]
2021-05-10 22:24 ` Kees Cook
2021-05-10 22:34 ` Kees Cook
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