From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73A9AC4321A for ; Wed, 3 Mar 2021 18:40:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 135F564EE1 for ; Wed, 3 Mar 2021 18:40:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1577205AbhCCRsa (ORCPT ); Wed, 3 Mar 2021 12:48:30 -0500 Received: from Galois.linutronix.de ([193.142.43.55]:44372 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235930AbhCCOwk (ORCPT ); Wed, 3 Mar 2021 09:52:40 -0500 From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1614783092; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=MtjHPmVHU8CBoanOm4MUbnVxPMgkXOhZVLNvYOhYD1U=; b=VBcI/SLxHW3/rrl47ew/1JWyoY45xuax+kmD5RjquJHm7U9Sn1D8oE4b7QLSCU3oMgFmGh z3le/JXubQcuGhD5P3QWRtC8u/GL9PIodvdGQSoxHEssTHnraDZQkOoUjqQ2K7krAgt1jV ZUSi+q6JLCC5m/r1WEBmAYhSQoYlMxzIRGuhQ0HGzQ6Wa6kkp5PoMzFJOPHwlYqLtGhcar eSOdZQ+cWJWboZrGQD2evWdypLgPG3WAV5WgUCcWUWpU2wFOuJRZBQOUVbGGM3V/3h8axz 4Cwd8tNoFr72IIN8/9Z9LaLpsmbNT5yKJkGbGkxToJQFZ6yK8RXjrkOnz7JTBw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1614783092; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=MtjHPmVHU8CBoanOm4MUbnVxPMgkXOhZVLNvYOhYD1U=; b=0rxHR11jus9SH3qP3+ZjgR0JVpoOyD9lIqBDYOp0NgjPsCQJHXgsc5gmmi5XyuQUGsMeSN J5ZbhmVR+ubbOYDQ== To: Feng Tang , Ingo Molnar , H Peter Anvin , Borislav Petkov , Peter Zijlstra , x86@kernel.org, linux-kernel@vger.kernel.org Cc: rui.zhang@intel.com, dave.hansen@intel.com, andi.kleen@intel.com, len.brown@intel.com, Feng Tang Subject: Re: [PATCH] x86/tsc: mark tsc reliable for qualified platforms In-Reply-To: <1614653572-19941-1-git-send-email-feng.tang@intel.com> References: <1614653572-19941-1-git-send-email-feng.tang@intel.com> Date: Wed, 03 Mar 2021 15:51:31 +0100 Message-ID: <878s7470jw.fsf@nanos.tec.linutronix.de> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 02 2021 at 10:52, Feng Tang wrote: > There are cases that tsc clocksource are wrongly judged as unstable by > clocksource watchdogs like hpet, acpi_pm or 'refined-jiffies'. While > there is hardly a general reliable way to check the validity of a > watchdog, and to protect the innocent tsc, Thomas Gleixner proposed [1]: > > "I'm inclined to lift that requirement when the CPU has: > > 1) X86_FEATURE_CONSTANT_TSC > 2) X86_FEATURE_NONSTOP_TSC > 3) X86_FEATURE_NONSTOP_TSC_S3 > 4) X86_FEATURE_TSC_ADJUST > 5) At max. 4 sockets > > After two decades of horrors we're finally at a point where TSC seems > to be halfway reliable and less abused by BIOS tinkerers. TSC_ADJUST > was really key as we can now detect even small modifications reliably > and the important point is that we can cure them as well (not pretty > but better than all other options)." > > So implement it with slight change as discussed in the thread, and be > more defensive to use maxim of 2 sockets. Can you please explain the slight change in the changelog? Thanks, tglx