From: Ben Dooks <ben.dooks@codethink.co.uk>
To: Conor Dooley <conor.dooley@microchip.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Daire McNamara <daire.mcnamara@microchip.com>,
Shravan Chippa <shravan.chippa@microchip.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Cyril Jean <Cyril.Jean@microchip.com>,
Lewis Hanly <lewis.hanly@microchip.com>,
Vattipalli Praveen <praveen.kumar@microchip.com>,
Wolfgang Grandegger <wg@aries-embedded.de>,
Hugh Breslin <hugh.breslin@microchip.com>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 6/9] riscv: dts: microchip: icicle: update pci address properties
Date: Tue, 30 Aug 2022 11:44:43 +0100 [thread overview]
Message-ID: <879a6823-6651-93cf-8500-661bedb050af@codethink.co.uk> (raw)
In-Reply-To: <20220830101803.1456180-7-conor.dooley@microchip.com>
On 30/08/2022 11:18, Conor Dooley wrote:
> For the v2022.09 reference design the PCI root port's data region has
> been moved to FIC1 from FIC0. This is a shorter path, allowing for
> higher clock rates and improved through-put. As a result, the address at
> which the PCIe's data region appears to the core complex has changed.
> The config region's address is unchanged.
Did this also fix the 32bit address apperture issue which plagued
getting pcie graphics cards sorted.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
next prev parent reply other threads:[~2022-08-30 10:45 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-30 10:17 [PATCH v2 0/9] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
2022-08-30 10:17 ` [PATCH v2 1/9] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
2022-08-30 10:17 ` [PATCH v2 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp Conor Dooley
2022-08-30 14:37 ` Krzysztof Kozlowski
2022-08-30 15:25 ` Conor.Dooley
2022-08-30 16:55 ` Krzysztof Kozlowski
2022-08-30 16:59 ` Conor.Dooley
2022-08-30 17:30 ` Krzysztof Kozlowski
2022-08-30 17:35 ` Conor.Dooley
2022-08-30 17:47 ` Krzysztof Kozlowski
2022-08-30 17:55 ` Conor.Dooley
2022-08-30 10:17 ` [PATCH v2 3/9] dt-bindings: riscv: microchip: document the sev kit Conor Dooley
2022-08-30 10:17 ` [PATCH v2 4/9] riscv: dts: microchip: add pci dma ranges for the icicle kit Conor Dooley
2022-08-30 10:18 ` [PATCH v2 5/9] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi Conor Dooley
2022-08-30 10:18 ` [PATCH v2 6/9] riscv: dts: microchip: icicle: update pci address properties Conor Dooley
2022-08-30 10:44 ` Ben Dooks [this message]
2022-08-30 12:06 ` Conor.Dooley
2022-08-30 10:18 ` [PATCH v2 7/9] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses Conor Dooley
2022-08-30 10:18 ` [PATCH v2 8/9] riscv: dts: microchip: add sevkit device tree Conor Dooley
2022-08-30 10:18 ` [PATCH v2 9/9] riscv: dts: microchip: add a devicetree for aries' m100pfsevp Conor Dooley
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