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From: Eric Anholt <eric@anholt.net>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: "open list\:DRM PANEL DRIVERS" <dri-devel@lists.freedesktop.org>,
	Russell King <linux@armlinux.org.uk>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	linux-clk <linux-clk@vger.kernel.org>,
	"linux-kernel\@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] drm/pl111: Register the clock divider and use it.
Date: Tue, 09 May 2017 11:18:56 -0700	[thread overview]
Message-ID: <87a86lgagf.fsf@eliezer.anholt.net> (raw)
In-Reply-To: <CACRpkdZUQX2MBiyd=m9P6HsxnNsf446RNR=R3-O_zm5GQXXOOg@mail.gmail.com>

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Linus Walleij <linus.walleij@linaro.org> writes:

> On Mon, May 8, 2017 at 9:33 PM, Eric Anholt <eric@anholt.net> wrote:
>
>> This is required for the panel to work on bcm911360, where CLCDCLK is
>> the fixed 200Mhz AXI41 clock.  The rate set is still passed up to the
>> CLCDCLK, for platforms that have a settable rate on that one.
>>
>> v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend on
>>     COMMON_CLK.
>>
>> Signed-off-by: Eric Anholt <eric@anholt.net>
>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Thanks.  Waiting on an ack from clock folks, then we'll be ready to go,
I think.

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  reply	other threads:[~2017-05-09 18:19 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-08 19:33 Eric Anholt
2017-05-08 21:42 ` Linus Walleij
2017-05-09 18:18   ` Eric Anholt [this message]
2017-05-10 12:33     ` Linus Walleij
2017-05-19  0:13 ` Stephen Boyd
2017-05-19 18:12   ` Eric Anholt

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