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From: Matthias Brugger <matthias.bgg@gmail.com>
To: Fei Shao <fshao@chromium.org>, James Lo <james.lo@mediatek.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
	Henry Chen <henryc.chen@mediatek.com>
Subject: Re: [PATCH 2/2] soc: mediatek: pwrap: add pwrap driver for MT8195 SoC
Date: Wed, 9 Jun 2021 10:06:27 +0200	[thread overview]
Message-ID: <87ab50ff-bae3-b2a3-1e54-642cdce3600d@gmail.com> (raw)
In-Reply-To: <CAC=S1nhUB=6y1SXUvAuhdj69S36FQnp9nr9V65TtS72pxuoRTg@mail.gmail.com>



On 09/06/2021 09:51, Fei Shao wrote:
> On Wed, Jun 2, 2021 at 7:21 PM James Lo <james.lo@mediatek.com> wrote:
>>
>> From: Henry Chen <henryc.chen@mediatek.com>
>>
>> MT8195 are highly integrated SoC and use PMIC_MT6359 for
>> power management. This patch adds pwrap master driver to
>> access PMIC_MT6359.
>>
>> Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
>> ---
>>  drivers/soc/mediatek/mtk-pmic-wrap.c | 35 ++++++++++++++++++++++++++++
>>  1 file changed, 35 insertions(+)
>>
>> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
>> index e4de75f35c33..952bc554f443 100644
>> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
>> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
>> @@ -961,6 +961,23 @@ static int mt8183_regs[] = {
>>         [PWRAP_WACS2_VLDCLR] =                  0xC28,
>>  };
>>
>> +static int mt8195_regs[] = {
>> +       [PWRAP_INIT_DONE2] =            0x0,
>> +       [PWRAP_STAUPD_CTRL] =           0x4C,
>> +       [PWRAP_TIMER_EN] =              0x3E4,
>> +       [PWRAP_INT_EN] =                0x420,
>> +       [PWRAP_INT_FLG] =               0x428,
>> +       [PWRAP_INT_CLR] =               0x42C,
>> +       [PWRAP_INT1_EN] =               0x450,
>> +       [PWRAP_INT1_FLG] =              0x458,
>> +       [PWRAP_INT1_CLR] =              0x45C,
>> +       [PWRAP_WACS2_CMD] =             0x880,
>> +       [PWRAP_SWINF_2_WDATA_31_0] =    0x884,
>> +       [PWRAP_SWINF_2_RDATA_31_0] =    0x894,
>> +       [PWRAP_WACS2_VLDCLR] =          0x8A4,
>> +       [PWRAP_WACS2_RDATA] =           0x8A8,
>> +};
>> +
>>  static int mt8516_regs[] = {
>>         [PWRAP_MUX_SEL] =               0x0,
>>         [PWRAP_WRAP_EN] =               0x4,
>> @@ -1066,6 +1083,7 @@ enum pwrap_type {
>>         PWRAP_MT8135,
>>         PWRAP_MT8173,
>>         PWRAP_MT8183,
>> +       PWRAP_MT8195,
>>         PWRAP_MT8516,
>>  };
>>
>> @@ -1525,6 +1543,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
>>                 break;
>>         case PWRAP_MT6873:
>>         case PWRAP_MT8183:
>> +       case PWRAP_MT8195:
>>                 break;
>>         }
>>
>> @@ -2025,6 +2044,19 @@ static const struct pmic_wrapper_type pwrap_mt8183 = {
>>         .init_soc_specific = pwrap_mt8183_init_soc_specific,
>>  };
>>
>> +static struct pmic_wrapper_type pwrap_mt8195 = {
>> +       .regs = mt8195_regs,
>> +       .type = PWRAP_MT8195,
>> +       .arb_en_all = 0x777f, /* NEED CONFIRM */
>> +       .int_en_all = 0x180000, /* NEED CONFIRM */
> 
> Please get the confirmative values here then send the next patch, thanks.
> 

Yes please. You can send this as a follow-up patch, otherwise I'd need to remove
this from my queue, as I have overseen the fact that not all values are confirmed.

Regards,
Matthias

  reply	other threads:[~2021-06-09  8:07 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-02 11:20 Add PMIC wrapper support for Mediatek MT8195 SoC IC James Lo
2021-06-02 11:20 ` [PATCH 1/2] dt-bindings: mediatek: add compatible for MT8195 pwrap James Lo
2021-06-02 11:20 ` [PATCH 2/2] soc: mediatek: pwrap: add pwrap driver for MT8195 SoC James Lo
2021-06-09  7:51   ` Fei Shao
2021-06-09  8:06     ` Matthias Brugger [this message]
2021-06-10  2:44       ` James Lo
2021-06-03 17:42 ` Add PMIC wrapper support for Mediatek MT8195 SoC IC Matthias Brugger

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