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Wed, 12 Jun 2024 14:19:15 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45CEJENw031149 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Jun 2024 14:19:14 GMT Received: from [10.226.59.182] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 12 Jun 2024 07:19:14 -0700 Message-ID: <87aecf24-cdbb-70d2-a3d1-8d1cacf18401@quicinc.com> Date: Wed, 12 Jun 2024 08:19:13 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.0 Subject: Re: [PATCH v2 1/2] bus: mhi: host: Import mux_id item Content-Language: en-US To: Manivannan Sadhasivam , Slark Xiao CC: , , , , , , References: <20240612093842.359805-1-slark_xiao@163.com> <20240612094609.GA58302@thinkpad> From: Jeffrey Hugo In-Reply-To: <20240612094609.GA58302@thinkpad> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: u8DihMomhUAk3P4xj0tSZnqG-fwtbN7y X-Proofpoint-ORIG-GUID: u8DihMomhUAk3P4xj0tSZnqG-fwtbN7y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-12_08,2024-06-12_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 spamscore=0 mlxscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1011 mlxlogscore=999 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406120102 On 6/12/2024 3:46 AM, Manivannan Sadhasivam wrote: > On Wed, Jun 12, 2024 at 05:38:42PM +0800, Slark Xiao wrote: > > Subject could be improved: > > bus: mhi: host: Add configurable mux_id for MBIM mode > >> For SDX72 MBIM mode, it starts data mux id from 112 instead of 0. >> This would lead to device can't ping outside successfully. >> Also MBIM side would report "bad packet session (112)". >> So we add a default mux_id value for SDX72. And this value >> would be transferred to wwan mbim side. >> >> Signed-off-by: Slark Xiao >> --- >> drivers/bus/mhi/host/pci_generic.c | 3 +++ >> include/linux/mhi.h | 2 ++ >> 2 files changed, 5 insertions(+) >> >> diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c >> index 0b483c7c76a1..9e9adf8320d2 100644 >> --- a/drivers/bus/mhi/host/pci_generic.c >> +++ b/drivers/bus/mhi/host/pci_generic.c >> @@ -53,6 +53,7 @@ struct mhi_pci_dev_info { >> unsigned int dma_data_width; >> unsigned int mru_default; >> bool sideband_wake; >> + unsigned int mux_id; >> }; >> >> #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ >> @@ -469,6 +470,7 @@ static const struct mhi_pci_dev_info mhi_foxconn_sdx72_info = { >> .dma_data_width = 32, >> .mru_default = 32768, >> .sideband_wake = false, >> + .mux_id = 112, >> }; >> >> static const struct mhi_channel_config mhi_mv3x_channels[] = { >> @@ -1035,6 +1037,7 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) >> mhi_cntrl->runtime_get = mhi_pci_runtime_get; >> mhi_cntrl->runtime_put = mhi_pci_runtime_put; >> mhi_cntrl->mru = info->mru_default; >> + mhi_cntrl->link_id = info->mux_id; > > Again, 'link_id' is just a WWAN term. Use 'mux_id' here also. Does this really belong in MHI? If this was DT, I don't think we would put this value in DT, but rather have the driver (MBIM) detect the device and code in the required value. Furthermore, if this is included in MHI, it seems to be a property of the channel, and not the controller. -Jeff