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From: James Morse <james.morse@arm.com>
To: Shiju Jose <shiju.jose@huawei.com>
Cc: linux-edac@vger.kernel.org, linux-acpi@vger.kernel.org,
	linux-kernel@vger.kernel.org, bp@alien8.de, tony.luck@intel.com,
	rjw@rjwysocki.net, lenb@kernel.org, rrichter@marvell.com,
	linuxarm@huawei.com, jonathan.cameron@huawei.com
Subject: Re: [RFC PATCH 0/4] EDAC/ghes: Add EDAC device for recording the CPU error count
Date: Fri, 6 Nov 2020 19:33:46 +0000	[thread overview]
Message-ID: <87b00978-8d5d-1917-b801-e6a36f704fb3@arm.com> (raw)
In-Reply-To: <20201105174233.1146-1-shiju.jose@huawei.com>

Hi Shiju,

On 05/11/2020 17:42, Shiju Jose wrote:
> For the firmware-first error handling on ARM64 hardware platforms,
> CPU cache corrected error count is not recorded.
> Create an CPU EDAC device and device blocks for the CPU caches
> for this purpose. The EDAC device blocks  are created based on the
> CPU caches information represented in the ACPI PPTT.

Using the PPTT won't work on x86 systems. Can we use the core-code's common data to learn
about caches: struct cpu_cacheinfo and struct cacheinfo ?


Thanks,

James

      parent reply	other threads:[~2020-11-06 19:33 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-05 17:42 Shiju Jose
2020-11-05 17:42 ` [RFC PATCH 1/4] ACPI: PPTT: Fix for a high level cache node detected in the low level Shiju Jose
2020-11-06 19:33   ` James Morse
2020-11-09 12:27     ` Jonathan Cameron
2020-11-09 15:59     ` Shiju Jose
2020-11-05 17:42 ` [RFC PATCH 2/4] ACPI: PPTT: Add function acpi_find_cache_info Shiju Jose
2020-11-05 17:42 ` [RFC PATCH 3/4] EDAC/ghes: Add EDAC device for the CPU caches Shiju Jose
2020-11-05 17:42 ` [RFC PATCH 4/4] ACPI / APEI: Add reporting ARM64 CPU cache corrected error count Shiju Jose
2020-11-06 19:33 ` James Morse [this message]

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