From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E59736E473 for ; Mon, 24 Aug 2026 16:32:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787589125; cv=none; b=aq7r+IwNXgPdRbkst7OZeJS6RLyJMEBO2b3mwy5pJo/H3X2d0dpDgvD9lepOcOAscJpbWFfZVhhwjJKjP1QaGk0/azNTWSmUioD4m9WJaPE/maH+xYtZnUAVnNn0grvbfN6wxA5YZn1N2JF7f66bH4J3nG0nWwqyQiVEulgk1YU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787589125; c=relaxed/simple; bh=rAYngJ1hQbRlQ4dPIr5bKiGR8gejEYQYKHSxaseDn74=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=Xc5SBfB/bXb1I3LC7x+0zE+qdP6fSJErg7rF5VgJgQp4s205m+wufnpS7frQHu7YBZ1ORvNswa6h8CelKDPx/Q4gya+v3RG/YmJCPQcEOJIgFaFMFF3a2+WKaXaYXKTJYJLvPqakOqJmjr1+IthERyAKWdThdClFGR0NpgDTSo8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VgyGBGEA; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VgyGBGEA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 24D721F00A3A; Mon, 24 Aug 2026 16:32:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1787589124; bh=LhrPuOzVrJQuV9lsTwwlx5y9U44yPp4q3nusbgeXo2I=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=VgyGBGEAkTpxfsmdtd5GPvM1gNtyyHb10JeS97wAjq4+4hbGFNYo1qaBNnBlXCWaV 6+iJntSXs6cDktovYK9IBgEgdsgsTt5xHbzGnShlUfrp6FfMdbvQdZoT91J8vrQBiu icCaPBW/bOsb1Cxmkmob09d8dO04wu+7kM/a8Faw8xJffPjJc1XjYdYu3uiwbmzeVV DLNmTiixbGIHdlteuwENpLOdx7axNnV+f1Z/XLgukSnA22dne+7fQraOaoDSAI3iKL 7P8VSrQ+V2QdEKduAxUe8/2ztfOQ0IDEGpaRH6y1LTorBVWuSWLxuPw/F1KwYz4V+f +MGuZkA4jrSPA== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wyXac-00000000lr9-1KhW; Mon, 24 Aug 2026 16:32:02 +0000 Date: Mon, 24 Aug 2026 17:34:34 +0100 Message-ID: <87bjaro4th.wl-maz@kernel.org> From: Marc Zyngier To: Li Dou Cc: tglx@kernel.org, radu@rendec.net, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] irqchip/gic-v3: Remove the ISB between AP0Rn and AP1Rn In-Reply-To: <20260824023403.1312-1-li8d6kernel@163.com> References: <20260824023403.1312-1-li8d6kernel@163.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: li8d6kernel@163.com, tglx@kernel.org, radu@rendec.net, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 24 Aug 2026 03:34:03 +0100, Li Dou wrote: > > ARM GICv3 specification says(in section 4.8.4 "System register access to > the Active Priorities registers"): > > an ISB is not required between each write to ICC_AP0R_EL1, > Secure ICC_AP1R_EL1, and Non-secure ICC_AP1R_EL1. > > It means we can use one ISB after resetting AP0Rn and AP1Rn for context > synchronization. So just remove the previous one. I'm afraid you have misinterpreted the spec. Within each of the AP0Rn, Secure AP1Rn and Non-Secure AP1Rn classes, for any value of 'n', there is no need for any synchronisation. However, between classes, you absolutely need an ISB. And this is the reason why, just above the note you quote: Writes to these registers in any order other than the following can result in UNPREDICTABLE behavior: 1. ICC_AP0R_EL1. 2. Secure ICC_AP1R_EL1. 3. Non-secure ICC_AP1R_EL1. While you can perfectly write each individual register of (1), (2) or (3) without any synchronisation, you absolutely must have a CSE *between* each of (1), (2) and (3). Linux being non-secure only, you only deal with (1) and (3), and you must have an ISB in between. Without it, reordering can happen and you end-up violating the above rule. To conclude, this patch does not optimise anything. Not only this is something that only happens once per CPU boot (aka *never*), it instead introduces a very subtle ordering bug. It therefore must not be applied. M. -- Jazz isn't dead. It just smells funny.