Hi Fabio, Fabio Estevam writes: > On Mon, Oct 6, 2025 at 6:22 PM Sergey Organov wrote: > >> It is built form multiple .dtsi, so I figure I attach the one after >> pre-processing stage. Please let me know if you'd prefer I rather >> manually insert all the custom .dtsi into a single .dts, and send that >> one instead. > > This format is hard to follow. > > To make things easier for debugging, you could create a minimal board > dts file with only UART and eMMC nodes to reproduce the problem. Please see attached minimum DTS. Maybe it misses something? Shouldn't DTS describe how eMMC chip is powered, provided it's powered from NXP MMPF0100F6ANES PMIC? I didn't find any hints in other DTS'es. > It's not clear to me the relationship between the ANATOP regulators > and the eMMC power on your board. Sheer mystery for me. The point of hang is not entirely deterministic either, that suggests it's some power problem indeed. It may hang after random line among the following depending on exact build and sometimes even from run-to-run: ... mmc0: SDHCI controller on 219c000.mmc [219c000.mmc] using ADMA Loading compiled-in X.509 certificates clk: Disabling unused clocks PM: genpd: Disabling unused power domains check access for rdinit=/init failed: -2, ignoring Waiting for root device /dev/mmcblk0p2... Also, I just tried to compile entire kernel with -DDEBUG, and it starts to see the eMMC, though still hangs not ever mounting the root FS: mmc0: SDHCI controller on 219c000.mmc [219c000.mmc] using ADMA Loading compiled-in X.509 certificates mmc0: new high speed DDR MMC card at address 0001 mmcblk0: mmc0:0001 IX2964 58.3 GiB mmcblk0: p1 p2 p3 p4 < p5 p6 > mmcblk0boot0: mmc0:0001 IX2964 4.00 MiB mmcblk0boot1: mmc0:0001 IX2964 4.00 MiB mmcblk0rpmb: mmc0:0001 IX2964 4.00 MiB, chardev (246:0) clk: Disabling unused clocks PM: genpd: Disabling unused power domains check access for rdinit=/init failed: -2, ignoring -- Sergey Organov