From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 746A0C4332F for ; Wed, 2 Nov 2022 08:03:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230394AbiKBID4 (ORCPT ); Wed, 2 Nov 2022 04:03:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230342AbiKBIDv (ORCPT ); Wed, 2 Nov 2022 04:03:51 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CD572714E for ; Wed, 2 Nov 2022 01:03:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667376230; x=1698912230; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version; bh=zUefAtldfFyX3o9cPUjfIV+mhHKwUmckyuph/rt9rAA=; b=ilJ1HYNiRiUWHBNH+IKNz14bpOhwj7l+0hB4WTH0Jpx31hf1QDsGztzx wRfNEa6PD35pz7eVxGhyBy4jxkY4IszsPQ0BY5APIN9HDg/cRioceDwoh ht4j/g7nDraVNVFyKXxKNE0Mz7DhxOXwa1CeYe5CBChvHIpvBHQhHUW9J uumCh69lfvqNAfOYtcNPS/mSvdBs90tT76Ws4myTWtWpEzhobFlESFXYV tAKBPdsyjXHkHu3p1WxIgxiMMN3vw0IYQw9nsMZFkIASuZq35DvRCzYja te04CeXRQJtBCIpN4KLEEAdUvI7EPcfaDiqMcPwJKReAJcN3wqAJPP+kY A==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="336018499" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="336018499" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 01:03:45 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="634167933" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="634167933" Received: from yhuang6-desk2.sh.intel.com (HELO yhuang6-desk2.ccr.corp.intel.com) ([10.238.208.55]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 01:03:40 -0700 From: "Huang, Ying" To: Michal Hocko Cc: Bharata B Rao , Aneesh Kumar K V , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Andrew Morton , Alistair Popple , Dan Williams , Dave Hansen , Davidlohr Bueso , Hesham Almatary , Jagdish Gediya , Johannes Weiner , Jonathan Cameron , Tim Chen , Wei Xu , Yang Shi Subject: Re: [RFC] memory tiering: use small chunk size and more tiers In-Reply-To: (Michal Hocko's message of "Wed, 2 Nov 2022 08:51:37 +0100") References: <578c9b89-10eb-1e23-8868-cdd6685d8d4e@linux.ibm.com> <877d0kk5uf.fsf@yhuang6-desk2.ccr.corp.intel.com> <59291b98-6907-0acf-df11-6d87681027cc@linux.ibm.com> <8735b8jy9k.fsf@yhuang6-desk2.ccr.corp.intel.com> <0d938c9f-c810-b10a-e489-c2b312475c52@amd.com> <87tu3oibyr.fsf@yhuang6-desk2.ccr.corp.intel.com> <07912a0d-eb91-a6ef-2b9d-74593805f29e@amd.com> <87leowepz6.fsf@yhuang6-desk2.ccr.corp.intel.com> <878rkuchpm.fsf@yhuang6-desk2.ccr.corp.intel.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) Date: Wed, 02 Nov 2022 16:02:54 +0800 Message-ID: <87bkppbx75.fsf@yhuang6-desk2.ccr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ascii Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Michal Hocko writes: > On Wed 02-11-22 08:39:49, Huang, Ying wrote: >> Michal Hocko writes: >> >> > On Mon 31-10-22 09:33:49, Huang, Ying wrote: >> > [...] >> >> In the upstream implementation, 4 tiers are possible below DRAM. That's >> >> enough for now. But in the long run, it may be better to define more. >> >> 100 possible tiers below DRAM may be too extreme. >> > >> > I am just curious. Is any configurations with more than couple of tiers >> > even manageable? I mean applications have been struggling even with >> > regular NUMA systems for years and vast majority of them is largerly >> > NUMA unaware. How are they going to configure for a more complex system >> > when a) there is no resource access control so whatever you aim for >> > might not be available and b) in which situations there is going to be a >> > demand only for subset of tears (GPU memory?) ? >> >> Sorry for confusing. I think that there are only several (less than 10) >> tiers in a system in practice. Yes, here, I suggested to define 100 (10 >> in the later text) POSSIBLE tiers below DRAM. My intention isn't to >> manage a system with tens memory tiers. Instead, my intention is to >> avoid to put 2 memory types into one memory tier by accident via make >> the abstract distance range of each memory tier as small as possible. >> More possible memory tiers, smaller abstract distance range of each >> memory tier. > > TBH I do not really understand how tweaking ranges helps anything. > IIUC drivers are free to assign any abstract distance so they will clash > without any higher level coordination. Yes. That's possible. Each memory tier corresponds to one abstract distance range. The larger the range is, the higher the possibility of clashing is. So I suggest to make the abstract distance range smaller to reduce the possibility of clashing. Best Regards, Huang, Ying