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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a1e8359sm942723166b.89.2025.08.05.10.40.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 05 Aug 2025 10:40:32 -0700 (PDT) Message-ID: <87c37d65-5ab1-4443-a428-dc3592062cdc@oss.qualcomm.com> Date: Tue, 5 Aug 2025 19:40:29 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] arm64: dts: qcom: sa8155: Add gear and rate limit properties to UFS To: Alim Akhtar , 'Manivannan Sadhasivam' Cc: 'Krzysztof Kozlowski' , 'Ram Kumar Dwivedi' , avri.altman@wdc.com, bvanassche@acm.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, James.Bottomley@hansenpartnership.com, martin.petersen@oracle.com, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <2a3c8867-7745-4f0a-8618-0f0f1bea1d14@kernel.org> <1701ec08-21bc-45b8-90bc-1cd64401abd8@kernel.org> <2nm7xurqgzrnffustrsmswy2rbug6geadaho42qlb7tr2jirlr@uw5gaery445y> <11ea828a-6d35-4ac6-a207-0284870c28fc@oss.qualcomm.com> <061b01dc062d$25c47800$714d6800$@samsung.com> <061c01dc062f$70ec34b0$52c49e10$@samsung.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <061c01dc062f$70ec34b0$52c49e10$@samsung.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: 8J9WX1fvzfDl2tFAoo_CoVRbzJdyQZ_p X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA1MDEyMiBTYWx0ZWRfX/vmIwDwsvZ6U i4vtctq8cG0DBV6Fn3wy7E1JLRPndsnJ5ljFC+YMtP5NO00Vre+uUfD4ei22lYUCFNN2cp56ejD DRZ2bqGa4F6K9fyEuMnJmiKVd9cAG2UgzAcFtBsqPDSx7AWjGL4IhPOlAUFAYueYCgbcziWIj/r VVVng7DRUpfLGJvzvqL6i5OY/kJvpVx0dEhoTioYmeJTzhNlqaD2DASJ+NrSAQB3jQKVyksB5cr e4hgn3CaBdfiRWqQtdq1Ve/86EpQDVNN6nsJ/RWnOX0VjdX4snfE6ZL5J+/fr9l5L0neHN6ZUrr As5MA4EPCl9DCIScyCUVrcX7Zs/C23fOdSIu2dSVvChkCEeS0VDBfj2rG7MH6YXre7z6FG3xPNs MvaoPh8HcU3gUwJUl4ctzdZIxVLz7las45eHP1QiUmbJpr60v5EPBqvRU0Xv2+Sz6YOQWGcK X-Proofpoint-GUID: 8J9WX1fvzfDl2tFAoo_CoVRbzJdyQZ_p X-Authority-Analysis: v=2.4 cv=a8Mw9VSF c=1 sm=1 tr=0 ts=68924212 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=VwQbUJbxAAAA:8 a=hD80L64hAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=JF9118EUAAAA:8 a=N54-gffFAAAA:8 a=bLk-5xynAAAA:8 a=yPCof4ZbAAAA:8 a=_u80KDpoiKaTEXzHalMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=TjNXssC_j7lpFel5tvFf:22 a=xVlTc564ipvMDusKsbsT:22 a=zSyb8xVVt2t83sZkrLMb:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-05_04,2025-08-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 phishscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 impostorscore=0 suspectscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2508050122 On 8/5/25 7:36 PM, Alim Akhtar wrote: > > >> -----Original Message----- >> From: 'Manivannan Sadhasivam' >> Sent: Tuesday, August 5, 2025 10:52 PM >> To: Alim Akhtar >> Cc: 'Konrad Dybcio' ; 'Krzysztof >> Kozlowski' ; 'Ram Kumar Dwivedi' >> ; avri.altman@wdc.com; >> bvanassche@acm.org; robh@kernel.org; krzk+dt@kernel.org; >> conor+dt@kernel.org; andersson@kernel.org; konradybcio@kernel.org; >> James.Bottomley@hansenpartnership.com; martin.petersen@oracle.com; >> agross@kernel.org; linux-arm-msm@vger.kernel.org; linux- >> scsi@vger.kernel.org; devicetree@vger.kernel.org; linux- >> kernel@vger.kernel.org >> Subject: Re: [PATCH 2/3] arm64: dts: qcom: sa8155: Add gear and rate limit >> properties to UFS >> >> On Tue, Aug 05, 2025 at 10:49:45PM GMT, Alim Akhtar wrote: >>> >>> >>>> -----Original Message----- >>>> From: Konrad Dybcio >>>> Sent: Tuesday, August 5, 2025 10:36 PM >>>> To: Manivannan Sadhasivam >>>> Cc: Krzysztof Kozlowski ; Ram Kumar Dwivedi >>>> ; alim.akhtar@samsung.com; >>>> avri.altman@wdc.com; bvanassche@acm.org; robh@kernel.org; >>>> krzk+dt@kernel.org; conor+dt@kernel.org; andersson@kernel.org; >>>> konradybcio@kernel.org; James.Bottomley@hansenpartnership.com; >>>> martin.petersen@oracle.com; agross@kernel.org; linux-arm- >>>> msm@vger.kernel.org; linux-scsi@vger.kernel.org; >>>> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org >>>> Subject: Re: [PATCH 2/3] arm64: dts: qcom: sa8155: Add gear and rate >>>> limit properties to UFS >>>> >>>> On 8/5/25 6:55 PM, Manivannan Sadhasivam wrote: >>>>> On Tue, Aug 05, 2025 at 03:16:33PM GMT, Konrad Dybcio wrote: >>>>>> On 8/1/25 2:19 PM, Manivannan Sadhasivam wrote: >>>>>>> On Fri, Aug 01, 2025 at 11:12:42AM GMT, Krzysztof Kozlowski wrote: >>>>>>>> On 01/08/2025 11:10, Ram Kumar Dwivedi wrote: >>>>>>>>> >>>>>>>>> >>>>>>>>> On 01-Aug-25 1:58 PM, Manivannan Sadhasivam wrote: >>>>>>>>>> On Thu, Jul 24, 2025 at 09:48:53AM GMT, Krzysztof Kozlowski >> wrote: >>>>>>>>>>> On 22/07/2025 18:11, Ram Kumar Dwivedi wrote: >>>>>>>>>>>> Add optional limit-hs-gear and limit-rate properties to the >>>>>>>>>>>> UFS node to support automotive use cases that require >>>>>>>>>>>> limiting the maximum Tx/Rx HS gear and rate due to hardware >> constraints. >>>>>>>>>>> >>>>>>>>>>> What hardware constraints? This needs to be clearly >> documented. >>>>>>>>>>> >>>>>>>>>> >>>>>>>>>> Ram, both Krzysztof and I asked this question, but you never >>>>>>>>>> bothered to reply, but keep on responding to other comments. >>>>>>>>>> This won't help you to get this series merged in any form. >>>>>>>>>> >>>>>>>>>> Please address *all* review comments before posting next >> iteration. >>>>>>>>> >>>>>>>>> Hi Mani, >>>>>>>>> >>>>>>>>> Apologies for the delay in responding. >>>>>>>>> I had planned to explain the hardware constraints in the next >>>> patchset’s commit message, which is why I didn’t reply earlier. >>>>>>>>> >>>>>>>>> To clarify: the limitations are due to customer board designs, >>>>>>>>> not our >>>> SoC. Some boards can't support higher gear operation, hence the need >>>> for optional limit-hs-gear and limit-rate properties. >>>>>>>>> >>>>>>>> >>>>>>>> That's vague and does not justify the property. You need to >>>>>>>> document instead hardware capabilities or characteristic. Or >>>>>>>> explain why they cannot. With such form I will object to your >>>>>>>> next >>>> patch. >>>>>>>> >>>>>>> >>>>>>> I had an offline chat with Ram and got clarified on what these >>>>>>> properties >>>> are. >>>>>>> The problem here is not with the SoC, but with the board design. >>>>>>> On some Qcom customer designs, both the UFS controller in the >>>>>>> SoC and the UFS device are capable of operating at higher gears (say >> G5). >>>>>>> But due to board constraints like poor thermal dissipation, >>>>>>> routing loss, the board cannot efficiently operate at the higher >> speeds. >>>>>>> >>>>>>> So the customers wanted a way to limit the gear speed (say G3) >>>>>>> and rate (say Mode-A) on the specific board DTS. >>>>>> >>>>>> I'm not necessarily saying no, but have you explored sysfs for this? >>>>>> >>>>>> I suppose it may be too late (if the driver would e.g. init the >>>>>> UFS at max gear/rate at probe time, it could cause havoc as it >>>>>> tries to load the userland).. >>>>>> >>>>> >>>>> If the driver tries to run with unsupported max gear speed/mode, >>>>> it will just crash with the error spit. >>>> >>>> OK >>>> >>>> just a couple related nits that I won't bother splitting into >>>> separate emails >>>> >>>> rate (mode? I'm seeing both names) should probably have dt-bindings >>>> defines while gear doesn't have to since they're called G >>>> anyway, with the bindings description strongly discouraging use, >>>> unless absolutely necessary (e.g. in the situation we have right >>>> there) >>>> >>>> I'd also assume the code should be moved into the ufs-common code, >>>> rather than making it ufs-qcom specific >>>> >>>> Konrad >>> Since this is a board specific constrains and not a SoC properties, have an >> option of handling this via bootloader is explored? >> >> Both board and SoC specific properties *should* be described in devicetree >> if they are purely describing the hardware. >> > Agreed, what I understood from above conversation is that, we are try to solve a very *specific* board problem here, > this does not looks like a generic problem to me and probably should be handled within the specific driver. Introducing generic solutions preemptively for problems that are simple in concept and can occur widely is good practice (although it's sometimes hard to gauge whether this is a one-off), as if the issue spreads a generic solution will appear at some point, but we'll have to keep supporting the odd ones as well Konrad