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Wed, 08 Jul 2026 04:19:50 -0700 (PDT) X-Received: by 2002:a17:90b:258f:b0:37f:bfcf:fdfb with SMTP id 98e67ed59e1d1-3892db5376emr1958242a91.8.1783509589584; Wed, 08 Jul 2026 04:19:49 -0700 (PDT) Received: from [10.92.199.168] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-387d2585f34sm2632880a91.17.2026.07.08.04.19.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Jul 2026 04:19:49 -0700 (PDT) Message-ID: <87c50f60-23d5-4987-a521-347614b2f596@oss.qualcomm.com> Date: Wed, 8 Jul 2026 16:49:42 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 09/19] clk: qcom: qcm2290: Set POLL_CFG_GDSCR flag for DISPCC and GPUCC GDSCs To: Dmitry Baryshkov Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Loic Poulain , Brian Masney , Dmitry Baryshkov , Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260703-shikra-dispcc-gpucc-v5-0-cc13826d4d5a@oss.qualcomm.com> <20260703-shikra-dispcc-gpucc-v5-9-cc13826d4d5a@oss.qualcomm.com> Content-Language: en-US From: Imran Shaik In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA4MDExMCBTYWx0ZWRfX0KkX4j+zydgd FxTv+M8q0Aiecjw9PFeniBpYYk75omEdTl4DiLAzs5lnUQhGu3dO+wIPf/I5MYeJOIECsIE65Jh y23fNTKP7iYQghH/3N6avdnuFAs5zQ3Tjw8H44R9bJuD7eZIs/C7H5n5u3O7BNWXlX8R3rTdd8b Lxm/wNakoeh/62z3waSa6W0pjAi9fwltPUwF2CLagfQUFw1m6UA57FZgB1ize0eHgBH/35sA4/i a5GAjFzloyzoNQEEs+VQNa6fx2LOG24s0LANiUjkDBJJfKXAL67WKbUxfTSqMg6x10O6kkPTsD7 JasHhcWtW7ahIoziZiki/2vxeO4WjG3hCWDyMzYMb+0UuJaaHi3NLNZ4EORKrd2jivWJ5kRt8I5 iudnpQPZDrP67RzkxLPHUabNpjWEOQ/mRy2JCq58YURpNP+oI4mk1L4TSWFIG9RUbmywYAQG5sb Cun0Z59gcsltxrCT8pg== X-Proofpoint-GUID: 34c3ek8z_fJdp5DY5y9P4z9HtkXmJ_aX X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA4MDExMCBTYWx0ZWRfXyHRO+U9d2ed+ hTv+MlGdf53fNu+vRUay4PnXOCoDQUD1yjetapChjLlgt454nzbThMICd3bk1kNc+xCS+t/rWec YLvtSIjCt0bkPyMbojzItijN05afUys= X-Proofpoint-ORIG-GUID: 34c3ek8z_fJdp5DY5y9P4z9HtkXmJ_aX X-Authority-Analysis: v=2.4 cv=Wf88rUhX c=1 sm=1 tr=0 ts=6a4e3256 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=Nhb7zu4WCAlJpChbyQcA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-08_01,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 bulkscore=0 impostorscore=0 malwarescore=0 spamscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607080110 On 04-07-2026 05:48 am, Dmitry Baryshkov wrote: > On Fri, Jul 03, 2026 at 12:01:31AM +0530, Imran Shaik wrote: >> On some targets, the GDSCR status bit may not reflect the actual state of > > Which targets? This is all about Agatti. > This is applicable to the latest targets. I will update the commit text here to mention Agatti specifically. Thanks, Imran >> the GDSC, instead the power on/off bits in CFG_GDSCR must be polled to >> determine the GDSC state correctly. Set POLL_CFG_GDSCR flag for the QCM2290 >> MDSS GDSC and GPUCC GX GDSC to ensure the correct GDSC status. This is not >> applicable for GPUCC CX GDSC, which relies on gds_hw_ctrl status. >> >> Signed-off-by: Imran Shaik >> --- >> drivers/clk/qcom/dispcc-qcm2290.c | 2 +- >> drivers/clk/qcom/gpucc-qcm2290.c | 2 +- >> 2 files changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c >> index 89a6cdd26217381cd44a515766363cf94d0aaeeb..6ee074555099ab72106cfae7c21adbd1b4a0fdac 100644 >> --- a/drivers/clk/qcom/dispcc-qcm2290.c >> +++ b/drivers/clk/qcom/dispcc-qcm2290.c >> @@ -467,7 +467,7 @@ static struct gdsc mdss_gdsc = { >> .name = "mdss_gdsc", >> }, >> .pwrsts = PWRSTS_OFF_ON, >> - .flags = HW_CTRL_TRIGGER, >> + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR, >> }; >> >> static struct gdsc *disp_cc_qcm2290_gdscs[] = { >> diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c >> index 66dea9d2a0e519dfc64d977ef107b5c875da3869..3b130f69bb93898ce49654f2366851a7c1c94524 100644 >> --- a/drivers/clk/qcom/gpucc-qcm2290.c >> +++ b/drivers/clk/qcom/gpucc-qcm2290.c >> @@ -313,7 +313,7 @@ static struct gdsc gpu_gx_gdsc = { >> }, >> .parent = &gpu_cx_gdsc.pd, >> .pwrsts = PWRSTS_OFF_ON, >> - .flags = CLAMP_IO | AON_RESET | SW_RESET, >> + .flags = POLL_CFG_GDSCR | CLAMP_IO | AON_RESET | SW_RESET, >> }; >> >> static struct clk_regmap *gpu_cc_qcm2290_clocks[] = { >> >> -- >> 2.34.1 >> >