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([2a0d:3344:2712:7e10:4d59:d956:544f:d65c]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4562e89c87esm50578175e9.33.2025.07.17.06.23.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Jul 2025 06:23:17 -0700 (PDT) Message-ID: <87cace03-dd5e-4624-9615-15f3babd1848@redhat.com> Date: Thu, 17 Jul 2025 15:23:16 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next v3 1/3] net: phy: qcom: Add PHY counter support To: Luo Jie , Andrew Lunn Cc: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250715-qcom_phy_counter-v3-0-8b0e460a527b@quicinc.com> <20250715-qcom_phy_counter-v3-1-8b0e460a527b@quicinc.com> <23ab18e6-517a-48da-926a-acfcaa76a4e7@quicinc.com> Content-Language: en-US From: Paolo Abeni In-Reply-To: <23ab18e6-517a-48da-926a-acfcaa76a4e7@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 7/16/25 12:15 PM, Luo Jie wrote: > On 7/16/2025 12:11 AM, Andrew Lunn wrote: >>> +int qcom_phy_update_stats(struct phy_device *phydev, >>> + struct qcom_phy_hw_stats *hw_stats) >>> +{ >>> + int ret; >>> + u32 cnt; >>> + >>> + /* PHY 32-bit counter for RX packets. */ >>> + ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_PKT_15_0); >>> + if (ret < 0) >>> + return ret; >>> + >>> + cnt = ret; >>> + >>> + ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_PKT_31_16); >>> + if (ret < 0) >>> + return ret; >> >> Does reading QCA808X_MMD7_CNT_RX_PKT_15_0 cause >> QCA808X_MMD7_CNT_RX_PKT_31_16 to latch? > > Checked with the hardware design team: The high 16-bit counter register > does not latch when reading the low 16 bits. > >> >> Sometimes you need to read the high part, the low part, and then >> reread the high part to ensure it has not incremented. But this is >> only needed if the hardware does not latch. >> >> Andrew > > Since the counter is configured to clear after reading, the clear action > takes priority over latching the count. This means that when reading the > low 16 bits, the high 16-bit counter value cannot increment, any new > packet events occurring during the read will be recorded after the > 16-bit counter is cleared. Out of sheer ignorance and language bias on my side, based on the above I would have assumed that the registers do latch ;) > Therefore, the current sequence for reading the counter is correct and > will not result in missed increments. Andrew, looks good? /P