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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: zXKVPnHKjrMFxSQum7i7m5xKSeuEuG5b X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAzNSBTYWx0ZWRfX4vK0YYOIypfT 4kmqtBSRTYx2vIjXBznMqIzCOKwORwqim2ED4epTnjklG6azjOCg0cgKRHZQuFfSYKV/yvLXJN2 lVFc3iCGvJKCMu/yGzgZKVl4pOmIRx94siARpjpJ179p5r+vUr4leKCi/cXostvFYQlp3j6vB07 bWpD1MvZkZTyEfQbrX/LSn6YwsuceueLBk9PYYxuNy0P0sZDkA3EpXkA5XTEd3ikYf5gy1X6JUq pJTTG6Mhbss/CzsKWS83S3KhXE+cnEloSDAJTstdXJd1cDDi2wWQ4vxteJc5p5C5TQXWXodd3kd S5ZJ2Gj27vDl/F6QObeic2HBhSQbPbe9HEDFSPdvTjOzKV0wT5ZTq3fKSzFiWLTF1UzU5iWbcYp kH5elZW/ X-Proofpoint-GUID: zXKVPnHKjrMFxSQum7i7m5xKSeuEuG5b X-Authority-Analysis: v=2.4 cv=N8UpF39B c=1 sm=1 tr=0 ts=68c02f90 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=2iJ5yM1ecYHLd0rZiA0A:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-09_01,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 malwarescore=0 clxscore=1015 bulkscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060035 On 9/3/2025 5:56 PM, Konrad Dybcio wrote: > On 8/21/25 8:55 PM, Akhil P Oommen wrote: >> From: Puranam V G Tejaswi >> >> Add gpu and gmu nodes for sa8775p chipset. As of now all >> SKUs have the same GPU fmax, so there is no requirement of >> speed bin support. >> >> Signed-off-by: Puranam V G Tejaswi >> Signed-off-by: Akhil P Oommen >> Reviewed-by: Dmitry Baryshkov >> --- >> arch/arm64/boot/dts/qcom/lemans.dtsi | 116 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 116 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi >> index 8ceb59742a9fc6562b2c38731ddabe3a549f7f35..8eac8d4719db9230105ad93ac22287850b6b007c 100644 >> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi >> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi >> @@ -1097,6 +1097,18 @@ ipcc: mailbox@408000 { >> #mbox-cells = <2>; >> }; >> >> + qfprom: efuse@784000 { >> + compatible = "qcom,sa8775p-qfprom", "qcom,qfprom"; >> + reg = <0x0 0x00784000 0x0 0x2410>; > > len = 0x3000 My bad. I missed these additional comments in this thread. Will extend this range to keep it 4K aligned. > > [...] > >> + gmu: gmu@3d6a000 { >> + compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; >> + reg = <0x0 0x03d6a000 0x0 0x34000>, > > This bleeds into GPU_CC, len should be 0x26000 > >> + <0x0 0x03de0000 0x0 0x10000>, >> + <0x0 0x0b290000 0x0 0x10000>; >> + reg-names = "gmu", "rscc", "gmu_pdc"; >> + interrupts = , >> + ; >> + interrupt-names = "hfi", "gmu"; >> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, >> + <&gpucc GPU_CC_CXO_CLK>, >> + <&gcc GCC_DDRSS_GPU_AXI_CLK>, >> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >> + <&gpucc GPU_CC_AHB_CLK>, >> + <&gpucc GPU_CC_HUB_CX_INT_CLK>, >> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; > > This clock only belongs in the SMMU node Not really. This is recommended for A663 GPU like other A660 based GPUs. I know it is not intuitive. Similarly, we used to vote GMU clk for GPU SMMU earlier. > >> + clock-names = "gmu", >> + "cxo", >> + "axi", >> + "memnoc", >> + "ahb", >> + "hub", >> + "smmu_vote"; >> + power-domains = <&gpucc GPU_CC_CX_GDSC>, >> + <&gpucc GPU_CC_GX_GDSC>; >> + power-domain-names = "cx", >> + "gx"; >> + iommus = <&adreno_smmu 5 0xc00>; >> + operating-points-v2 = <&gmu_opp_table>; >> + >> + gmu_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-200000000 { >> + opp-hz = /bits/ 64 <200000000>; > > 500 MHz @ RPMH_REGULATOR_LEVEL_SVS, 200 isn't even present in the clock driver > Ack. I guess this is fine. Hopefully GMU won't explode. :) -Akhil > Konrad