From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Jon Hunter <jonathanh@nvidia.com>
Cc: Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <mwalle@kernel.org>,
Takahiro Kuwano <takahiro.kuwano@infineon.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Nicolas Ferre <nicolas.ferre@microchip.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Claudiu Beznea <claudiu.beznea@tuxon.dev>,
Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Randy Dunlap <rdunlap@infradead.org>,
Steam Lin <STLin2@winbond.com>,
Hsin-Yi Wang <hsinyi@chromium.org>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
linux-mtd@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>
Subject: Re: [PATCH v5 03/25] mtd: spi-nor: Refactor Read Status/Write Status support
Date: Thu, 10 Sep 2026 11:57:11 +0200 [thread overview]
Message-ID: <87ecf1sa2w.fsf@bootlin.com> (raw)
In-Reply-To: <b78b8e6a-2fab-489f-aa1b-a2ab23051794@nvidia.com> (Jon Hunter's message of "Thu, 10 Sep 2026 05:38:01 +0100")
Hello Jon,
On 10/09/2026 at 05:38:01 +01, Jon Hunter <jonathanh@nvidia.com> wrote:
> Hi Miguel,
>
> On 04/09/2026 19:12, Miquel Raynal wrote:
>
> ...
>
>> This is a really hard to review patch, it is big, full of changes
>> everywhere, but I cannot really split it further. The commit log is
>> really important, it tries to explain the steps I went through when
>> trying to refactor the whole QE/SR handling for which I received
>> feedback from Michael, Tudor and Sashiko.
>> Ideally we could expect test coverage of each case:
>> - BFPT_DWORD15_QER_NONE: Probably not needed
>> - BFPT_DWORD15_QER_SR2_BIT1_BUGGY: Expected from Hsin-Yi (flag is being
>> renamed _NO_1B_WR)
>> - BFPT_DWORD15_QER_SR2_BIT1_NO_RD: Tested with a chip re-enabling RDCR
>> in a fixup
>> - BFPT_DWORD15_QER_SR1_BIT6: TBD
>> - BFPT_DWORD15_QER_SR2_BIT7: TBD
>> - BFPT_DWORD15_QER_SR2_BIT1: TBD
>> - BFPT_DWORD15_QER_SR2_BIT1_1B: Done.
>> There will probably be breakages on older chips. These cannot be
>> guessed because they are not properly listed in manufacturer
>> fixups (yet). If we want a cleanup/simplification, we will have to cope
>> with this risk.
>> I hope the diff stats will motivate people to have a look and report
>> their testing.
>> I will also eagerly monitor Sashiko's output which will probably be
>> very useful to catch niche weird cases where these changes might break.
>
>
> Since this landed in -next I am seeing a flash/boot issue on one of our
> Jetson boards. This board, Tegra234 Jetson Orin Nano
> (tegra234-p3768-0000+p3767-0005.dts), uses a QSPI flash device and the
> kernel is used to flash this device. Following this commit, on boot I
> now see ...
>
> spi-nor spi0.0: probe with driver spi-nor failed with error -22
Thanks for catching this early! I'll get back to you with a proposal
very soon.
Miquèl
next prev parent reply other threads:[~2026-09-10 9:57 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 18:12 [PATCH v5 00/25] mtd: spi-nor: QE handling cleanup + fixup reworks + Winbond RV chips addition Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 01/25] mtd: spi-nor: Rename BFPT_DWORD15_QER_SR2_BIT1_BUGGY Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 02/25] mtd: spi-nor: Create a structure containing the flash opcodes Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 03/25] mtd: spi-nor: Refactor Read Status/Write Status support Miquel Raynal
2026-09-10 4:38 ` Jon Hunter
2026-09-10 9:57 ` Miquel Raynal [this message]
2026-09-11 9:09 ` Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 04/25] mtd: spi-nor: Add support for the new JESD216 rev F QER field Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 05/25] mtd: spi-nor: Create the concept of fixup table with match function Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 06/25] mtd: spi-nor: Move the fixup flags into the fixup list Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 07/25] mtd: spi-nor: Create an indirection on the part name Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 08/25] mtd: spi-nor: Move the SFDP header structure to a C header Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 09/25] mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-Q/N parts Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 10/25] mtd: spi-nor: winbond: Add support for W25Q32RV-Q/N Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 11/25] mtd: spi-nor: winbond: Add support for W25Q64RV-Q/N Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 12/25] mtd: spi-nor: winbond: Add support for W25Q12RV-Q/N Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 13/25] mtd: spi-nor: winbond: Add support for W25Q25RV-Q/N Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 14/25] mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 15/25] mtd: spi-nor: winbond: Add support for W25Q01RV-Q/N Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 16/25] mtd: spi-nor: winbond: Add support for W25Q02RV-Q/N Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 17/25] mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-M parts Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 18/25] mtd: spi-nor: winbond: Add support for W25Q32RV-M Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 19/25] mtd: spi-nor: winbond: Add support for W25Q64RV-M Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 20/25] mtd: spi-nor: winbond: Add support for W25Q12RV-M Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 21/25] mtd: spi-nor: winbond: Add support for W25Q25RV-M Miquel Raynal
2026-09-04 18:12 ` [PATCH v5 22/25] mtd: spi-nor: winbond: Add support for W25Q51RV-M Miquel Raynal
2026-09-04 18:13 ` [PATCH v5 23/25] mtd: spi-nor: winbond: Add support for W25Q01RV-M Miquel Raynal
2026-09-04 18:13 ` [PATCH v5 24/25] mtd: spi-nor: winbond: Add support for W25Q02RV-M Miquel Raynal
2026-09-04 18:13 ` [PATCH v5 25/25] mtd: spi-nor: debugfs: Expose SR opcodes and QE mask Miquel Raynal
2026-09-07 7:46 ` [PATCH v5 00/25] mtd: spi-nor: QE handling cleanup + fixup reworks + Winbond RV chips addition Michael Walle
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87ecf1sa2w.fsf@bootlin.com \
--to=miquel.raynal@bootlin.com \
--cc=STLin2@winbond.com \
--cc=alexandre.belloni@bootlin.com \
--cc=claudiu.beznea@tuxon.dev \
--cc=corbet@lwn.net \
--cc=hsinyi@chromium.org \
--cc=jonathanh@nvidia.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=linux-tegra@vger.kernel.org \
--cc=mwalle@kernel.org \
--cc=nicolas.ferre@microchip.com \
--cc=pratyush@kernel.org \
--cc=rdunlap@infradead.org \
--cc=richard@nod.at \
--cc=skhan@linuxfoundation.org \
--cc=takahiro.kuwano@infineon.com \
--cc=thomas.petazzoni@bootlin.com \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®