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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF0002BA4D.mail.protection.outlook.com (10.167.242.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Fri, 21 Jun 2024 05:46:29 +0000 Received: from BLRRASHENOY1 (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 21 Jun 2024 00:46:26 -0500 From: Gautham R.Shenoy To: Perry Yuan , , , CC: , , , , Subject: Re: [PATCH v12 7/9] cpufreq: amd-pstate: fix the MSR highest perf will be reset issue while cpb boost off In-Reply-To: References: Date: Fri, 21 Jun 2024 11:16:24 +0530 Message-ID: <87frt6voen.fsf@BLR-5CG11610CF.amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4D:EE_|SJ2PR12MB7893:EE_ X-MS-Office365-Filtering-Correlation-Id: 5e6e6c6c-944a-4bee-0091-08dc91b57fa5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|82310400023|36860700010|1800799021|376011; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2024 05:46:29.5614 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e6e6c6c-944a-4bee-0091-08dc91b57fa5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7893 Perry Yuan writes: > From: Perry Yuan > > Select the min perf to fix the highest perf value while update pstate > CPPC request MSR register, here it needs to limit the max perf value when > CPU boost is disabled in case of that highest perf value in the MSR will be > reset to original highest perf value which cause the BOOST control > failed. Perhaps we could rephrase this as "When Core Performance Boost is disabled by the user, the CPPC_REQ.max_perf should not exceed the nominal_perf since by definition the frequencies between nominal_perf and the highest_perf are in the boost range. Fix this in amd_pstate_update()" Also change the subject to "cpufreq:amd-pstate: Cap the CPPC.max_perf to nominal_perf if CPB is off" ? > > Signed-off-by: Perry Yuan > Acked-by: Huang Rui > Reviewed-by: Mario Limonciello Other than that, Reviewed-by: Gautham R. Shenoy > --- > drivers/cpufreq/amd-pstate.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 299e52d4b17e..f2ccef089acc 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -524,6 +524,7 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, > u32 des_perf, u32 max_perf, bool fast_switch, int gov_flags) > { > u64 prev = READ_ONCE(cpudata->cppc_req_cached); > + u32 nominal_perf = READ_ONCE(cpudata->nominal_perf); > u64 value = prev; > > min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, > @@ -543,6 +544,10 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, > value &= ~AMD_CPPC_DES_PERF(~0L); > value |= AMD_CPPC_DES_PERF(des_perf); > > + /* limit the max perf when core performance boost feature is disabled */ > + if (!amd_pstate_global_params.cpb_boost) > + max_perf = min_t(unsigned long, nominal_perf, max_perf); > + > value &= ~AMD_CPPC_MAX_PERF(~0L); > value |= AMD_CPPC_MAX_PERF(max_perf); > > -- > 2.34.1 -- Thanks and Regards gautham.