Re: [PATCH] mtd: spi-nor: Fix quad-enable for flashes with QER bit in SR1

[Miquel Raynal <miquel.raynal@bootlin.com>]

On 11/09/2026 at 11:19:39 +02, Miquel Raynal <miquel.raynal@bootlin.com> wrote:

>>> -	ret = spi_nor_read_sr1_and_sr2(nor, sr);
>>> +	if (qe_mask[0])
>>> +		ret = spi_nor_read_sr1(nor, sr);
>>> +	else
>>> +		ret = spi_nor_read_sr1_and_sr2(nor, sr);
>>
>> Shouldn't that be the other way around?
>>
>> +	if (qe_mask[1])
>> +		ret = spi_nor_read_sr1_and_sr2(nor, sr);
>> +	else
>> +		ret = spi_nor_read_sr1(nor, sr);
>>
>> I know qe_mask won't be spread across two SRs. Just to be
>> correct and make it easier to grok.
>
> Why is the second version easier to parse? First version is maybe more
> future proof since we are treating a specific case. Because either it is
> a specific chip (Mxic) or we end up in the more common case. There is
> only one QER entry for qe_mask[0], many for qe_mask[1], and chances are
> that in the future we will mostly see new chips only using a qe_mask[1]
> mask. So having this in the else doesn't sound so strange to me? I also
> don't think we will ever see masks spanning the two registers.

The problem still persists because there is the check which also fails
reading SR2.

Michael, we moved to swp.c that handling, introducing a "careful"
revision, was this actually relevant? Shouldn't we have the handling of
the lack of SR2 read back into the main core like before?

Possible steps forward:
1- Add extra logic in the "and_check" helper, kind of duplicating what
   is in the swp.c file (not my favourite)
2- Move the "careful" handling (which does not return errors when a
   register read is absent) back from swp.c into core.c.

What do you prefer?

Thanks,
Miquèl