From: Miquel Raynal <miquel.raynal@bootlin.com>
To: "Rob Herring (Arm)" <robh@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] dt-bindings: phy: Convert marvell,comphy-cp110 to DT schema
Date: Mon, 09 Jun 2025 10:01:50 +0200 [thread overview]
Message-ID: <87ikl51gy9.fsf@bootlin.com> (raw)
In-Reply-To: <20250607212605.743176-1-robh@kernel.org> (Rob Herring's message of "Sat, 7 Jun 2025 16:26:03 -0500")
Hi Rob,
Thanks for the conversion.
On 07/06/2025 at 16:26:03 -05, "Rob Herring (Arm)" <robh@kernel.org> wrote:
> Convert the Marvell CP110 combo PHY binding to DT schema format. It's a
> straight forward conversion.
>
> Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
[...]
> +properties:
> + compatible:
> + enum:
> + - marvell,comphy-cp110
> + - marvell,comphy-a3700
> +
> + reg:
> + minItems: 1
> + items:
> + - description: Generic COMPHY registers
Would you mind to add "(Armada 7k/8k)" here? This information was in the
description and got lost. Armada 7k/8k had (IIRC) a number of
Application Processors and Co-Processors, it might not be
straightforward to guess what "cp110" means to people not familiar with
Marvell naming otherwise?
> + - description: Lane 1 (PCIe/GbE) registers (Armada 3700)
> + - description: Lane 0 (USB3/GbE) registers (Armada 3700)
> + - description: Lane 2 (SATA/USB3) registers (Armada 3700)
> +
> + reg-names:
> + minItems: 1
minItems should probably be 4 as it is only required (and mandatory) for
the marvell,comphy-a3700 compatible? I do not think we intended to ask
for a reg-names property when there was just one entry (see
armada-cp11x.dtsi).
> + items:
> + - const: comphy
> + - const: lane1_pcie_gbe
> + - const: lane0_usb3_gbe
> + - const: lane2_sata_usb3
> +
> + '#address-cells':
> + const: 1
Should be required?
> +
> + '#size-cells':
> + const: 0
Should be required as well?
> +
> + clocks:
> + maxItems: 3
> + description: Reference clocks for CP110; MG clock, MG Core clock, AXI clock
> +
> + clock-names:
> + items:
> + - const: mg_clk
> + - const: mg_core_clk
> + - const: axi_clk
> +
> + marvell,system-controller:
> + description: Phandle to the Marvell system controller (CP110 only)
> + $ref: /schemas/types.yaml#/definitions/phandle
> +
> +patternProperties:
> + '^phy@[0-2]$':
Technically, these nodes are also mandatory, I don't remember if we can
mark them as such in the "required" section though.
> + description: A COMPHY lane child node
> + type: object
> + additionalProperties: false
> +
> + properties:
> + reg:
> + description: COMPHY lane number
> +
> + '#phy-cells':
> + const: 1
> +
> + required:
> + - reg
> + - '#phy-cells'
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
Thanks,
Miquèl
prev parent reply other threads:[~2025-06-09 8:23 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-07 21:26 Rob Herring (Arm)
2025-06-09 8:01 ` Miquel Raynal [this message]
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