From: "Huang, Ying" <ying.huang@intel.com>
To: Gregory Price <gourry@gourry.net>
Cc: Dan Williams <dan.j.williams@intel.com>,
Dave Jiang <dave.jiang@intel.com>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Alejandro Lucero <alucerop@amd.com>
Subject: Re: [RFC 3/5] cxl: Separate coherence from target type
Date: Fri, 11 Oct 2024 10:40:57 +0800 [thread overview]
Message-ID: <87iktz9xae.fsf@yhuang6-desk2.ccr.corp.intel.com> (raw)
In-Reply-To: <87plojnxog.fsf@yhuang6-desk2.ccr.corp.intel.com> (Ying Huang's message of "Wed, 02 Oct 2024 08:41:35 +0800")
"Huang, Ying" <ying.huang@intel.com> writes:
> Gregory Price <gourry@gourry.net> writes:
>
>> On Wed, Sep 25, 2024 at 10:46:45AM +0800, Huang Ying wrote:
[snip]
>
>>> @@ -1925,6 +1933,29 @@ static int cxl_region_attach(struct cxl_region *cxlr,
>>> return -ENXIO;
>>> }
>>>
>>> + /* Set the coherence of region to that of the first endpoint */
>>> + if (cxlr->coherence == CXL_DECODER_INVALIDCOH) {
>>> + unsigned long flags = cxlrd->cxlsd.cxld.flags;
>>> + enum cxl_decoder_coherence coherence = cxled->cxld.coherence;
>>> +
>>> + cxlr->coherence = coherence;
>>> + if ((coherence == CXL_DECODER_HOSTONLYCOH &&
>>> + !(flags & CXL_DECODER_F_HOSTONLYCOH)) ||
>>> + (coherence == CXL_DECODER_DEVCOH &&
>>> + !(flags & CXL_DECODER_F_DEVCOH))) {
>>
>> silly nit but my gut tells me we can make this less ugly.
>> Not a blocker though.
>
> Yes. This looks urgly. Will think about how to improve it.
Reviewed the code again. However, I don't have any idea to improve
this. Do you have some suggestion?
>>> + dev_dbg(&cxlr->dev,
>>> +"%s:%s endpoint coherence: %d isn't supported by root decoder: %#lx\n",
>>> + dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev),
>>> + coherence, flags);
>>> + return -ENXIO;
>>> + }
>
--
Best Regards,
Huang, Ying
next prev parent reply other threads:[~2024-10-11 2:44 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-25 2:46 [RFC 0/5] cxl: Preparation of type2 accelerators support Huang Ying
2024-09-25 2:46 ` [RFC 1/5] cxl: Rename ACPI_CEDT_CFMWS_RESTRICT_TYPE2/TYPE3 Huang Ying
2024-10-01 2:48 ` Davidlohr Bueso
2024-10-01 13:43 ` Gregory Price
2024-09-25 2:46 ` [RFC 2/5] cxl: Rename CXL_DECODER_HOSTONLYMEM/DEVMEM Huang Ying
2024-10-01 3:01 ` Davidlohr Bueso
2024-10-01 13:45 ` Gregory Price
2024-09-25 2:46 ` [RFC 3/5] cxl: Separate coherence from target type Huang Ying
2024-10-01 13:53 ` Gregory Price
2024-10-02 0:41 ` Huang, Ying
2024-10-11 2:40 ` Huang, Ying [this message]
2024-10-02 21:15 ` Ben Cheatham
2024-10-03 1:13 ` Huang, Ying
2024-09-25 2:46 ` [RFC 4/5] cxl: Set type of region to that of the first endpoint Huang Ying
2024-10-01 13:56 ` Gregory Price
2024-10-02 0:40 ` Huang, Ying
2024-10-02 21:15 ` Ben Cheatham
2024-10-03 1:12 ` Huang, Ying
2024-10-03 14:28 ` Ben Cheatham
2024-09-25 2:46 ` [RFC 5/5] cxl: Avoid to create dax regions for type2 accelerators Huang Ying
2024-10-01 13:57 ` Gregory Price
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