From: Marc Zyngier <maz@kernel.org>
To: Jianmin Lv <lvjianmin@loongson.cn>
Cc: Thomas Gleixner <tglx@linutronix.de>,
linux-kernel@vger.kernel.org, Hanjun Guo <guohanjun@huawei.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Huacai Chen <chenhuacai@loongson.cn>
Subject: Re: [PATCH V12 01/10] APCI: irq: Add support for multiple GSI domains
Date: Wed, 15 Jun 2022 08:14:29 +0100 [thread overview]
Message-ID: <87k09ipfe2.wl-maz@kernel.org> (raw)
In-Reply-To: <1655273250-23495-2-git-send-email-lvjianmin@loongson.cn>
On Wed, 15 Jun 2022 07:07:21 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
> From: Marc Zyngier <maz@kernel.org>
>
> In an unfortunate departure from the ACPI spec, the LoongArch
> architecture split its GSI space across multiple interrupt
> controllers.
>
> In order to be able to reuse sthe core code and prevent
> architectures from reinventing an already square wheel, offer
> the arch code the ability to register a dispatcher function
> that will return the domain fwnode for a given GSI.
>
> The ARM GIC drivers are updated to support this (with a single
> domain, as intended).
>
> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
I don't think this tag is appropriate here.
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> Cc: Hanjun Guo <guohanjun@huawei.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> ---
> drivers/acpi/irq.c | 40 +++++++++++++++++++++++-----------------
> drivers/irqchip/irq-gic-v3.c | 18 ++++++++++++------
> drivers/irqchip/irq-gic.c | 18 ++++++++++++------
> include/linux/acpi.h | 2 +-
> 4 files changed, 48 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c
> index c68e694..b7460ab 100644
> --- a/drivers/acpi/irq.c
> +++ b/drivers/acpi/irq.c
> @@ -12,7 +12,7 @@
>
> enum acpi_irq_model_id acpi_irq_model;
>
> -static struct fwnode_handle *acpi_gsi_domain_id;
> +static struct fwnode_handle *(*acpi_get_gsi_domain_id)(u32 gsi);
>
> /**
> * acpi_gsi_to_irq() - Retrieve the linux irq number for a given GSI
> @@ -26,10 +26,7 @@
> */
> int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
> {
> - struct irq_domain *d = irq_find_matching_fwnode(acpi_gsi_domain_id,
> - DOMAIN_BUS_ANY);
> -
> - *irq = irq_find_mapping(d, gsi);
> + *irq = acpi_register_gsi(NULL, gsi, -1, -1);
What is this?
- This wasn't part of my initial patch, and randomly changing patches
without mentioning it isn't acceptable
- you *cannot* trigger a registration here, as this isn't what the API
advertises
- what makes you think that passing random values (NULL, -1... )to
acpi_register_gsi() is an acceptable thing to do?
The original patch had:
@@ -26,8 +26,10 @@ static struct fwnode_handle *acpi_gsi_domain_id;
*/
int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
{
- struct irq_domain *d = irq_find_matching_fwnode(acpi_gsi_domain_id,
- DOMAIN_BUS_ANY);
+ struct irq_domain *d;
+
+ d = irq_find_matching_fwnode(acpi_get_gsi_domain_id(gsi),
+ DOMAIN_BUS_ANY);
*irq = irq_find_mapping(d, gsi);
/*
and I don't think it needs anything else. If something breaks, let's
discuss it, but don't abuse the API nor the fact that I usually don't
review my own patches to sneak things in...
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2022-06-15 7:15 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-15 6:07 [PATCH V12 00/10] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
2022-06-15 6:07 ` [PATCH V12 01/10] APCI: irq: Add support for multiple GSI domains Jianmin Lv
2022-06-15 7:14 ` Marc Zyngier [this message]
2022-06-15 9:28 ` Jianmin Lv
2022-06-18 10:36 ` Marc Zyngier
2022-06-20 2:46 ` Jianmin Lv
2022-06-25 9:34 ` Jianmin Lv
2022-06-27 7:32 ` Marc Zyngier
2022-06-27 8:00 ` Jianmin Lv
2022-06-28 7:42 ` Hanjun Guo
2022-06-28 8:45 ` Jianmin Lv
2022-06-28 9:12 ` Hanjun Guo
2022-06-15 9:43 ` Jianmin Lv
2022-06-15 6:07 ` [PATCH V12 02/10] genirq/generic_chip: export irq_unmap_generic_chip Jianmin Lv
2022-06-15 6:07 ` [PATCH V12 03/10] irqchip: Add LoongArch CPU interrupt controller support Jianmin Lv
2022-06-18 10:59 ` Marc Zyngier
2022-06-20 3:06 ` Jianmin Lv
2022-06-15 6:07 ` [PATCH V12 04/10] irqchip: create library file for LoongArch irqchip driver Jianmin Lv
2022-06-18 17:22 ` Marc Zyngier
2022-06-20 3:12 ` Jianmin Lv
2022-06-27 7:34 ` Marc Zyngier
2022-06-27 8:04 ` Jianmin Lv
2022-06-15 6:07 ` [PATCH V12 05/10] irqchip/loongson-pch-pic: Add ACPI init support Jianmin Lv
2022-06-15 6:07 ` [PATCH V12 06/10] irqchip/loongson-pch-msi: " Jianmin Lv
2022-06-15 6:07 ` [PATCH V12 07/10] irqchip/loongson-htvec: " Jianmin Lv
2022-06-18 10:39 ` [PATCH V12 00/10] irqchip: Add LoongArch-related irqchip drivers Marc Zyngier
2022-06-20 2:28 ` Jianmin Lv
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87k09ipfe2.wl-maz@kernel.org \
--to=maz@kernel.org \
--cc=chenhuacai@loongson.cn \
--cc=guohanjun@huawei.com \
--cc=jiaxun.yang@flygoat.com \
--cc=linux-kernel@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=lvjianmin@loongson.cn \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
Powered by JetHome