From: Namhyung Kim <namhyung@kernel.org>
To: Stephane Eranian <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, peterz@infradead.org,
mingo@elte.hu, ak@linux.intel.com, acme@redhat.com,
jolsa@redhat.com, ming.m.lin@intel.com
Subject: Re: [Patch v1 06/10] perf/x86: add support for PEBS Precise Store
Date: Wed, 31 Oct 2012 14:21:21 +0900 [thread overview]
Message-ID: <87pq3z5i9a.fsf@sejong.aot.lge.com> (raw)
In-Reply-To: <1351523752-4215-7-git-send-email-eranian@google.com> (Stephane Eranian's message of "Mon, 29 Oct 2012 16:15:48 +0100")
On Mon, 29 Oct 2012 16:15:48 +0100, Stephane Eranian wrote:
> This patch adds support for PEBS Precise Store
> which is available on Intel Sandy Bridge and
> Ivy Bridge processors.
>
> To use Precise store, the proper PEBS event
> must be used: mem_trans_retired:precise_stores.
> For the perf tool, the generic mem-stores event
> exported via sysfs can be used directly.
Just trivial nitpicks..
>
> Signed-off-by: Stephane Eranian <eranian@google.com>
> ---
[snip]
> @@ -486,6 +524,7 @@ struct event_constraint intel_snb_pebs_event_constraints[] = {
> INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
> INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
> INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
> + INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
> INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
> INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
> INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
> @@ -500,6 +539,7 @@ struct event_constraint intel_ivb_pebs_event_constraints[] = {
> INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
> INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
> INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
> + INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
White-space damaged? Oh, it seems already broken with spaces.
> INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
> INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
> INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
[snip]
> @@ -672,7 +715,7 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
> /*
> * if PEBS-LL or PreciseStore
> */
> - if (fll) {
> + if (fll || fst) {
> if (sample_type & PERF_SAMPLE_ADDR)
> data.addr = pebs->dla;
>
> @@ -688,6 +731,8 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
> if (sample_type & PERF_SAMPLE_DSRC) {
> if (fll)
> data.dsrc.val = load_latency_data(pebs->dse);
> + else if (fst)
Looks like it can be converted to a plain 'else'.
Thanks,
Namhyung
next prev parent reply other threads:[~2012-10-31 5:21 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-29 15:15 [Patch v1 00/10] perf: add memory access sampling support Stephane Eranian
2012-10-29 15:15 ` [Patch v1 01/10] perf/x86: improve sysfs event mapping with event string Stephane Eranian
2012-10-29 19:25 ` Andi Kleen
2012-10-29 15:15 ` [Patch v1 02/10] perf/x86: add flags to event constraints Stephane Eranian
2012-10-29 15:15 ` [Patch v1 03/10] perf: add generic memory sampling interface Stephane Eranian
2012-10-29 15:15 ` [Patch v1 04/10] perf/x86: add memory profiling via PEBS Load Latency Stephane Eranian
2012-10-29 15:23 ` Peter Zijlstra
2012-10-29 15:24 ` Stephane Eranian
2012-10-29 15:35 ` Peter Zijlstra
2012-10-29 15:39 ` Stephane Eranian
2012-10-29 15:38 ` Peter Zijlstra
2012-10-29 15:43 ` Stephane Eranian
2012-10-29 15:44 ` Peter Zijlstra
2012-10-29 19:42 ` Andi Kleen
2012-10-29 20:39 ` Stephane Eranian
2012-10-29 20:44 ` Peter Zijlstra
2012-10-29 21:16 ` Andi Kleen
2012-10-29 21:32 ` Stephane Eranian
2012-10-29 21:56 ` Andi Kleen
2012-10-30 8:43 ` Namhyung Kim
2012-10-29 15:15 ` [Patch v1 05/10] perf/x86: export PEBS load latency threshold register to sysfs Stephane Eranian
2012-10-29 15:15 ` [Patch v1 06/10] perf/x86: add support for PEBS Precise Store Stephane Eranian
2012-10-29 15:40 ` Peter Zijlstra
2012-10-29 15:44 ` Stephane Eranian
2012-10-31 5:21 ` Namhyung Kim [this message]
2012-10-31 13:28 ` Stephane Eranian
2012-10-29 15:15 ` [Patch v1 07/10] perf tools: add mem access sampling core support Stephane Eranian
2012-10-29 16:55 ` Andi Kleen
2012-10-29 17:00 ` Stephane Eranian
2012-10-31 5:51 ` Namhyung Kim
2012-10-31 13:30 ` Stephane Eranian
2012-10-29 15:15 ` [Patch v1 08/10] perf report: add support for mem access profiling Stephane Eranian
2012-10-31 6:01 ` Namhyung Kim
2012-10-29 15:15 ` [Patch v1 09/10] perf record: " Stephane Eranian
2012-10-29 15:15 ` [Patch v1 10/10] perf tools: add new mem command for memory " Stephane Eranian
2012-10-31 6:57 ` Namhyung Kim
2012-10-31 14:23 ` Stephane Eranian
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