From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755896AbbI3J6U (ORCPT ); Wed, 30 Sep 2015 05:58:20 -0400 Received: from mga14.intel.com ([192.55.52.115]:5868 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753627AbbI3J6R (ORCPT ); Wed, 30 Sep 2015 05:58:17 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,611,1437462000"; d="scan'208";a="780778317" From: Alexander Shishkin To: Mathieu Poirier , gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, acme@kernel.org, mingo@redhat.com, corbet@lwn.net Cc: adrian.hunter@intel.com, zhang.chunyan@linaro.org, mike.leach@arm.com, tor@ti.com, al.grant@arm.com, pawel.moll@arm.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 01/20] coresight: etm3x: splitting 'etm_enable_hw()' operations In-Reply-To: <1442593594-10665-2-git-send-email-mathieu.poirier@linaro.org> References: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> <1442593594-10665-2-git-send-email-mathieu.poirier@linaro.org> User-Agent: Notmuch/0.20.2 (http://notmuchmail.org) Emacs/24.5.1 (x86_64-pc-linux-gnu) Date: Wed, 30 Sep 2015 12:58:11 +0300 Message-ID: <87r3lgjkjw.fsf@ashishki-desk.ger.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Mathieu Poirier writes: > -static void etm_enable_hw(void *info) > +static void etm_power_up_cpu(void *info) > { > - int i; > - u32 etmcr; > - struct etm_drvdata *drvdata = info; > + struct coresight_device *csdev = info; > + struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + > + WARN_ON(drvdata->cpu != smp_processor_id()); Maybe WARN_ON_ONCE() is sufficient here (and other similar places). > +static void etm_power_down_cpu(void *info) > +{ > + struct coresight_device *csdev = info; > + struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + > + WARN_ON(drvdata->cpu != smp_processor_id()); Likewise. > +/** > + * etm_configure_cpu - configure ETM registers > + * @csdev - the etm that needs to be configure. > + * > + * Applies a configuration set to the ETM registers _without_ enabling the > + * tracer. This function needs to be executed on the CPU who's tracer is > + * being configured. > + */ > +static void etm_configure_cpu(void *info) > +{ > + int i; > + u32 etmcr; > + struct coresight_device *csdev = info; > + struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + > + WARN_ON(drvdata->cpu != smp_processor_id()); Likewise. > + > + CS_UNLOCK(drvdata->base); > etm_set_prog(drvdata); > > etmcr = etm_readl(drvdata, ETMCR); > - etmcr &= (ETMCR_PWD_DWN | ETMCR_ETM_PRG); > etmcr |= drvdata->port_size; > etm_writel(drvdata, drvdata->ctrl | etmcr, ETMCR); > etm_writel(drvdata, drvdata->trigger_event, ETMTRIGGER); Most of these things can also be bypassed, as at least initially perf events won't be using trigger/sequencer configurations, so we could simply clear all these things out when a first perf event is created (which would also disallow any sysfs poking around the etm/etb) and not worry about them in the pmu callbacks. Regards, -- Alex